Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
47 /* Local-Access Registers & ECM Registers */
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
191 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
192 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
193 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
194 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
195 u32 powar0; /* PCIX Outbound Window Attrs 0 */
197 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
198 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
199 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
200 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
201 u32 powar1; /* PCIX Outbound Window Attrs 1 */
203 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
204 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
205 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
206 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
207 u32 powar2; /* PCIX Outbound Window Attrs 2 */
209 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
210 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
211 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
212 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
213 u32 powar3; /* PCIX Outbound Window Attrs 3 */
215 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
216 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
217 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
218 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
219 u32 powar4; /* PCIX Outbound Window Attrs 4 */
298 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
300 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
365 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
419 u32 tr64; /* TX & RX 64-byte Frame Counter */
420 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
421 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
422 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
423 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
424 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
425 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
1160 /* SCC1-SCC4 */
1262 u32 pwdcsr; /* Port-Write and Doorbell CSR */
1273 /* Extended Features Space: 1x/4x LP-Serial Port registers */
1283 /* Extended Features Space: 1x/4x LP-Serial registers */
1287 u32 pltoccsr; /* Port Link Time-out CCSR */
1288 u32 prtoccsr; /* Port Response Time-out CCSR */
1324 /* Implementation Space: General Port-Common */
1329 u32 epwisr; /* Error / Port-Write Interrupt SR */
1341 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1370 u32 rowtar; /* RapidIO Outbound Window TAR */
1371 u32 rowtear; /* RapidIO Outbound Window TEAR */
1374 u32 rowar; /* RapidIO Outbound Attributes Register */
1375 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1400 u32 omr; /* Outbound Mode Register */
1401 u32 osr; /* Outbound Status Register */
1402 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1403 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1404 u32 eosar; /* Extended Outbound Unit Source AR */
1405 u32 osar; /* Outbound Unit Source AR */
1406 u32 odpr; /* Outbound Destination Port Register */
1407 u32 odatr; /* Outbound Destination Attributes Register */
1408 u32 odcr; /* Outbound Doubleword Count Register */
1409 u32 eodqepar; /* Extended Outbound DQ EPAR */
1410 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1411 u32 oretr; /* Outbound Retry Error Threshold Register */
1412 u32 omgr; /* Outbound Multicast Group Register */
1413 u32 omlr; /* Outbound Multicast List Register */
1415 u32 imr; /* Outbound Mode Register */
1429 u32 odmr; /* Outbound Doorbell Mode Register */
1430 u32 odsr; /* Outbound Doorbell Status Register */
1432 u32 oddpr; /* Outbound Doorbell Destination Port */
1433 u32 oddatr; /* Outbound Doorbell Destination AR */
1435 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1443 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1447 u32 pwmr; /* Port-Write Mode Register */
1448 u32 pwsr; /* Port-Write Status Register */
1449 u32 epwqbar; /* Extended Port-Write Queue BAR */
1450 u32 pwqbar; /* Port-Write Queue Base Address Register */
1509 * blocks - if there is more than one CPC, we expect these to be
1510 * contiguous 4k regions
1557 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1577 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1595 u8 res_008[0x20-0x8];
1596 u32 gpporcr1; /* General-purpose POR configuration */
1597 u32 gpporcr2; /* General-purpose POR configuration 2 */
1603 u8 res_02c[0x70-0x2c];
2122 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2198 u32 gpporcr; /* General-purpose POR configuration */
2213 u32 gpoutdr; /* General-purpose output data */
2216 u32 gpindr; /* General-purpose input data */
2579 u8 res_18[0x20-0x18];
2581 u8 res_40[0x90-0x40];
2583 u8 res_94[0xa0-0x94];
2585 u8 res_a4[0xb0-0xa4];
2587 u8 res_b4[0xe0-0xb4];
2593 u8 res_f4[0x100-0xf4];
2596 u8 res_104[0x120-0x104];
2598 u8 res_200[0x800-0x200];
2609 u8 res_824[0x840-0x824];
2611 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
3057 u8 res_0c[500];/* 0x00c - 0x1ff */
3090 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3094 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3098 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3117 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3139 u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */