include/asm/immap_85xx.h

621 typedef struct ccsr_pic {  struct
622 	u8	res1[64];
623 	u32	ipidr0;		/* Interprocessor IRQ Dispatch 0 */
624 	u8	res2[12];
625 	u32	ipidr1;		/* Interprocessor IRQ Dispatch 1 */
626 	u8	res3[12];
627 	u32	ipidr2;		/* Interprocessor IRQ Dispatch 2 */
628 	u8	res4[12];
629 	u32	ipidr3;		/* Interprocessor IRQ Dispatch 3 */
630 	u8	res5[12];
631 	u32	ctpr;		/* Current Task Priority */
632 	u8	res6[12];
633 	u32	whoami;		/* Who Am I */
634 	u8	res7[12];
635 	u32	iack;		/* IRQ Acknowledge */
636 	u8	res8[12];
637 	u32	eoi;		/* End Of IRQ */
638 	u8	res9[3916];
639 	u32	frr;		/* Feature Reporting */
640 	u8	res10[28];
641 	u32	gcr;		/* Global Configuration */
644 	u8	res11[92];
645 	u32	vir;		/* Vendor Identification */
646 	u8	res12[12];
647 	u32	pir;		/* Processor Initialization */
648 	u8	res13[12];
649 	u32	ipivpr0;	/* IPI Vector/Priority 0 */
650 	u8	res14[12];
651 	u32	ipivpr1;	/* IPI Vector/Priority 1 */
652 	u8	res15[12];
653 	u32	ipivpr2;	/* IPI Vector/Priority 2 */
654 	u8	res16[12];
655 	u32	ipivpr3;	/* IPI Vector/Priority 3 */
656 	u8	res17[12];
657 	u32	svr;		/* Spurious Vector */
658 	u8	res18[12];
659 	u32	tfrr;		/* Timer Frequency Reporting */
660 	u8	res19[12];
661 	u32	gtccr0;		/* Global Timer Current Count 0 */
662 	u8	res20[12];
663 	u32	gtbcr0;		/* Global Timer Base Count 0 */
664 	u8	res21[12];
665 	u32	gtvpr0;		/* Global Timer Vector/Priority 0 */
666 	u8	res22[12];
667 	u32	gtdr0;		/* Global Timer Destination 0 */
668 	u8	res23[12];
669 	u32	gtccr1;		/* Global Timer Current Count 1 */
670 	u8	res24[12];
671 	u32	gtbcr1;		/* Global Timer Base Count 1 */
672 	u8	res25[12];
673 	u32	gtvpr1;		/* Global Timer Vector/Priority 1 */
674 	u8	res26[12];
675 	u32	gtdr1;		/* Global Timer Destination 1 */
676 	u8	res27[12];
677 	u32	gtccr2;		/* Global Timer Current Count 2 */
678 	u8	res28[12];
679 	u32	gtbcr2;		/* Global Timer Base Count 2 */
680 	u8	res29[12];
681 	u32	gtvpr2;		/* Global Timer Vector/Priority 2 */
682 	u8	res30[12];
683 	u32	gtdr2;		/* Global Timer Destination 2 */
684 	u8	res31[12];
685 	u32	gtccr3;		/* Global Timer Current Count 3 */
686 	u8	res32[12];
687 	u32	gtbcr3;		/* Global Timer Base Count 3 */
688 	u8	res33[12];
689 	u32	gtvpr3;		/* Global Timer Vector/Priority 3 */
690 	u8	res34[12];
691 	u32	gtdr3;		/* Global Timer Destination 3 */
692 	u8	res35[268];
693 	u32	tcr;		/* Timer Control */
694 	u8	res36[12];
695 	u32	irqsr0;		/* IRQ_OUT Summary 0 */
696 	u8	res37[12];
697 	u32	irqsr1;		/* IRQ_OUT Summary 1 */
698 	u8	res38[12];
699 	u32	cisr0;		/* Critical IRQ Summary 0 */
700 	u8	res39[12];
701 	u32	cisr1;		/* Critical IRQ Summary 1 */
702 	u8	res40[188];
703 	u32	msgr0;		/* Message 0 */
704 	u8	res41[12];
705 	u32	msgr1;		/* Message 1 */
706 	u8	res42[12];
707 	u32	msgr2;		/* Message 2 */
708 	u8	res43[12];
709 	u32	msgr3;		/* Message 3 */
710 	u8	res44[204];
711 	u32	mer;		/* Message Enable */
712 	u8	res45[12];
713 	u32	msr;		/* Message Status */
714 	u8	res46[60140];
715 	u32	eivpr0;		/* External IRQ Vector/Priority 0 */
716 	u8	res47[12];
717 	u32	eidr0;		/* External IRQ Destination 0 */
718 	u8	res48[12];
719 	u32	eivpr1;		/* External IRQ Vector/Priority 1 */
720 	u8	res49[12];
721 	u32	eidr1;		/* External IRQ Destination 1 */
722 	u8	res50[12];
723 	u32	eivpr2;		/* External IRQ Vector/Priority 2 */
724 	u8	res51[12];
725 	u32	eidr2;		/* External IRQ Destination 2 */
726 	u8	res52[12];
727 	u32	eivpr3;		/* External IRQ Vector/Priority 3 */
728 	u8	res53[12];
729 	u32	eidr3;		/* External IRQ Destination 3 */
730 	u8	res54[12];
731 	u32	eivpr4;		/* External IRQ Vector/Priority 4 */
732 	u8	res55[12];
733 	u32	eidr4;		/* External IRQ Destination 4 */
734 	u8	res56[12];
735 	u32	eivpr5;		/* External IRQ Vector/Priority 5 */
736 	u8	res57[12];
737 	u32	eidr5;		/* External IRQ Destination 5 */
738 	u8	res58[12];
739 	u32	eivpr6;		/* External IRQ Vector/Priority 6 */
740 	u8	res59[12];
741 	u32	eidr6;		/* External IRQ Destination 6 */
742 	u8	res60[12];
743 	u32	eivpr7;		/* External IRQ Vector/Priority 7 */
744 	u8	res61[12];
745 	u32	eidr7;		/* External IRQ Destination 7 */
746 	u8	res62[12];
747 	u32	eivpr8;		/* External IRQ Vector/Priority 8 */
748 	u8	res63[12];
749 	u32	eidr8;		/* External IRQ Destination 8 */
750 	u8	res64[12];
751 	u32	eivpr9;		/* External IRQ Vector/Priority 9 */
752 	u8	res65[12];
753 	u32	eidr9;		/* External IRQ Destination 9 */
754 	u8	res66[12];
755 	u32	eivpr10;	/* External IRQ Vector/Priority 10 */
756 	u8	res67[12];
757 	u32	eidr10;		/* External IRQ Destination 10 */
758 	u8	res68[12];
759 	u32	eivpr11;	/* External IRQ Vector/Priority 11 */
760 	u8	res69[12];
761 	u32	eidr11;		/* External IRQ Destination 11 */
762 	u8	res70[140];
763 	u32	iivpr0;		/* Internal IRQ Vector/Priority 0 */
764 	u8	res71[12];
765 	u32	iidr0;		/* Internal IRQ Destination 0 */
766 	u8	res72[12];
767 	u32	iivpr1;		/* Internal IRQ Vector/Priority 1 */
768 	u8	res73[12];
769 	u32	iidr1;		/* Internal IRQ Destination 1 */
770 	u8	res74[12];
771 	u32	iivpr2;		/* Internal IRQ Vector/Priority 2 */
772 	u8	res75[12];
773 	u32	iidr2;		/* Internal IRQ Destination 2 */
774 	u8	res76[12];
775 	u32	iivpr3;		/* Internal IRQ Vector/Priority 3 */
776 	u8	res77[12];
777 	u32	iidr3;		/* Internal IRQ Destination 3 */
778 	u8	res78[12];
779 	u32	iivpr4;		/* Internal IRQ Vector/Priority 4 */
780 	u8	res79[12];
781 	u32	iidr4;		/* Internal IRQ Destination 4 */
782 	u8	res80[12];
783 	u32	iivpr5;		/* Internal IRQ Vector/Priority 5 */
784 	u8	res81[12];
785 	u32	iidr5;		/* Internal IRQ Destination 5 */
786 	u8	res82[12];
787 	u32	iivpr6;		/* Internal IRQ Vector/Priority 6 */
788 	u8	res83[12];
789 	u32	iidr6;		/* Internal IRQ Destination 6 */
790 	u8	res84[12];
791 	u32	iivpr7;		/* Internal IRQ Vector/Priority 7 */
792 	u8	res85[12];
793 	u32	iidr7;		/* Internal IRQ Destination 7 */
794 	u8	res86[12];
795 	u32	iivpr8;		/* Internal IRQ Vector/Priority 8 */
796 	u8	res87[12];
797 	u32	iidr8;		/* Internal IRQ Destination 8 */
798 	u8	res88[12];
799 	u32	iivpr9;		/* Internal IRQ Vector/Priority 9 */
800 	u8	res89[12];
801 	u32	iidr9;		/* Internal IRQ Destination 9 */
802 	u8	res90[12];
803 	u32	iivpr10;	/* Internal IRQ Vector/Priority 10 */
804 	u8	res91[12];
805 	u32	iidr10;		/* Internal IRQ Destination 10 */
806 	u8	res92[12];
807 	u32	iivpr11;	/* Internal IRQ Vector/Priority 11 */
808 	u8	res93[12];
809 	u32	iidr11;		/* Internal IRQ Destination 11 */
810 	u8	res94[12];
811 	u32	iivpr12;	/* Internal IRQ Vector/Priority 12 */
812 	u8	res95[12];
813 	u32	iidr12;		/* Internal IRQ Destination 12 */
814 	u8	res96[12];
815 	u32	iivpr13;	/* Internal IRQ Vector/Priority 13 */
816 	u8	res97[12];
817 	u32	iidr13;		/* Internal IRQ Destination 13 */
818 	u8	res98[12];
819 	u32	iivpr14;	/* Internal IRQ Vector/Priority 14 */
820 	u8	res99[12];
821 	u32	iidr14;		/* Internal IRQ Destination 14 */
822 	u8	res100[12];
823 	u32	iivpr15;	/* Internal IRQ Vector/Priority 15 */
824 	u8	res101[12];
825 	u32	iidr15;		/* Internal IRQ Destination 15 */
826 	u8	res102[12];
827 	u32	iivpr16;	/* Internal IRQ Vector/Priority 16 */
828 	u8	res103[12];
829 	u32	iidr16;		/* Internal IRQ Destination 16 */
830 	u8	res104[12];
831 	u32	iivpr17;	/* Internal IRQ Vector/Priority 17 */
832 	u8	res105[12];
833 	u32	iidr17;		/* Internal IRQ Destination 17 */
834 	u8	res106[12];
835 	u32	iivpr18;	/* Internal IRQ Vector/Priority 18 */
836 	u8	res107[12];
837 	u32	iidr18;		/* Internal IRQ Destination 18 */
838 	u8	res108[12];
839 	u32	iivpr19;	/* Internal IRQ Vector/Priority 19 */
840 	u8	res109[12];
841 	u32	iidr19;		/* Internal IRQ Destination 19 */
842 	u8	res110[12];
843 	u32	iivpr20;	/* Internal IRQ Vector/Priority 20 */
844 	u8	res111[12];
845 	u32	iidr20;		/* Internal IRQ Destination 20 */
846 	u8	res112[12];
847 	u32	iivpr21;	/* Internal IRQ Vector/Priority 21 */
848 	u8	res113[12];
849 	u32	iidr21;		/* Internal IRQ Destination 21 */
850 	u8	res114[12];
851 	u32	iivpr22;	/* Internal IRQ Vector/Priority 22 */
852 	u8	res115[12];
853 	u32	iidr22;		/* Internal IRQ Destination 22 */
854 	u8	res116[12];
855 	u32	iivpr23;	/* Internal IRQ Vector/Priority 23 */
856 	u8	res117[12];
857 	u32	iidr23;		/* Internal IRQ Destination 23 */
858 	u8	res118[12];
859 	u32	iivpr24;	/* Internal IRQ Vector/Priority 24 */
860 	u8	res119[12];
861 	u32	iidr24;		/* Internal IRQ Destination 24 */
862 	u8	res120[12];
863 	u32	iivpr25;	/* Internal IRQ Vector/Priority 25 */
864 	u8	res121[12];
865 	u32	iidr25;		/* Internal IRQ Destination 25 */
866 	u8	res122[12];
867 	u32	iivpr26;	/* Internal IRQ Vector/Priority 26 */
868 	u8	res123[12];
869 	u32	iidr26;		/* Internal IRQ Destination 26 */
870 	u8	res124[12];
871 	u32	iivpr27;	/* Internal IRQ Vector/Priority 27 */
872 	u8	res125[12];
873 	u32	iidr27;		/* Internal IRQ Destination 27 */
874 	u8	res126[12];
875 	u32	iivpr28;	/* Internal IRQ Vector/Priority 28 */
876 	u8	res127[12];
877 	u32	iidr28;		/* Internal IRQ Destination 28 */
878 	u8	res128[12];
879 	u32	iivpr29;	/* Internal IRQ Vector/Priority 29 */
880 	u8	res129[12];
881 	u32	iidr29;		/* Internal IRQ Destination 29 */
882 	u8	res130[12];
883 	u32	iivpr30;	/* Internal IRQ Vector/Priority 30 */
884 	u8	res131[12];
885 	u32	iidr30;		/* Internal IRQ Destination 30 */
886 	u8	res132[12];
887 	u32	iivpr31;	/* Internal IRQ Vector/Priority 31 */
888 	u8	res133[12];
889 	u32	iidr31;		/* Internal IRQ Destination 31 */
890 	u8	res134[4108];
891 	u32	mivpr0;		/* Messaging IRQ Vector/Priority 0 */
892 	u8	res135[12];
893 	u32	midr0;		/* Messaging IRQ Destination 0 */
894 	u8	res136[12];
895 	u32	mivpr1;		/* Messaging IRQ Vector/Priority 1 */
896 	u8	res137[12];
897 	u32	midr1;		/* Messaging IRQ Destination 1 */
898 	u8	res138[12];
899 	u32	mivpr2;		/* Messaging IRQ Vector/Priority 2 */
923 } ccsr_pic_t;  argument