include/asm/immap_83xx.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2004-2011 Freescale Semiconductor, Inc.
55 	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
56 	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
143 	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
144 	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
149 	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
150 	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
161 	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
162 	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
229 	u32 dat;		/* data register */
252 	u32 pdat;		/* Data Register */
304 	u32 ddr_data_init;	/* SDRAM Data Initialization */
314 	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
315 	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
316 	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
318 	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
319 	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
320 	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
328 	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
357 	u32 res0[0xC];		/* 0x0-0x29 reseverd */
360 	u32 res1[0x6];		/* 0x38-0x49 reserved */
366 	u32 res2;		/* 0x64-0x67 reserved */
368 	u32 res3[0x5];		/* 0x6C-0x79 reserved */
371 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
615  * TDM
622  * TDM DMAC
747 	tdm83xx_t		tdm;		/* TDM Controller */  member
754 	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
953 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)