Lines Matching defs:immap
629 typedef struct immap { struct
630 sysconf83xx_t sysconf; /* System configuration */
631 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
632 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
633 rtclk83xx_t pit; /* Periodic Interval Timer */
634 gtm83xx_t gtm[2]; /* Global Timers Module */
635 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
636 arbiter83xx_t arbiter; /* System Arbiter Registers */
637 reset83xx_t reset; /* Reset Module */
638 clk83xx_t clk; /* System Clock Module */
639 pmc83xx_t pmc; /* Power Management Control Module */
640 gpio83xx_t gpio[2]; /* General purpose I/O module */
641 u8 res0[0x200];
642 u8 dll_ddr[0x100];
643 u8 dll_lbc[0x100];
667 } immap_t; argument
683 typedef struct immap { argument
684 sysconf83xx_t sysconf; /* System configuration */
685 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
686 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
687 rtclk83xx_t pit; /* Periodic Interval Timer */
688 gtm83xx_t gtm[2]; /* Global Timers Module */
689 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
690 arbiter83xx_t arbiter; /* System Arbiter Registers */
691 reset83xx_t reset; /* Reset Module */
715 } immap_t; argument
718 typedef struct immap { argument
719 sysconf83xx_t sysconf; /* System configuration */
720 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
721 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
722 rtclk83xx_t pit; /* Periodic Interval Timer */
723 gtm83xx_t gtm[2]; /* Global Timers Module */
724 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
725 arbiter83xx_t arbiter; /* System Arbiter Registers */
726 reset83xx_t reset; /* Reset Module */
727 clk83xx_t clk; /* System Clock Module */
728 pmc83xx_t pmc; /* Power Management Control Module */
729 gpio83xx_t gpio[1]; /* General purpose I/O module */
730 u8 res0[0x1300];
731 ddr83xx_t ddr; /* DDR Memory Controller Memory */
732 fsl_i2c_t i2c[2]; /* I2C Controllers */
733 u8 res1[0x1300];
734 duart83xx_t duart[2]; /* DUART */
735 u8 res2[0x900];
736 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
760 } immap_t; argument
763 typedef struct immap { argument
764 sysconf83xx_t sysconf; /* System configuration */
765 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
766 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
767 rtclk83xx_t pit; /* Periodic Interval Timer */
768 gtm83xx_t gtm[2]; /* Global Timers Module */
769 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
770 arbiter83xx_t arbiter; /* System Arbiter Registers */
771 reset83xx_t reset; /* Reset Module */
772 clk83xx_t clk; /* System Clock Module */
773 pmc83xx_t pmc; /* Power Management Control Module */
774 gpio83xx_t gpio[2]; /* General purpose I/O module */
775 u8 res0[0x1200];
776 ddr83xx_t ddr; /* DDR Memory Controller Memory */
777 fsl_i2c_t i2c[2]; /* I2C Controllers */
778 u8 res1[0x1300];
779 duart83xx_t duart[2]; /* DUART */
780 u8 res2[0x900];
804 } immap_t; argument
807 typedef struct immap { argument
808 sysconf83xx_t sysconf; /* System configuration */
809 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
810 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
811 rtclk83xx_t pit; /* Periodic Interval Timer */
812 u8 res0[0x200];
813 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
814 arbiter83xx_t arbiter; /* System Arbiter Registers */
815 reset83xx_t reset; /* Reset Module */
816 clk83xx_t clk; /* System Clock Module */
817 pmc83xx_t pmc; /* Power Management Control Module */
818 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
819 u8 res1[0x300];
820 u8 dll_ddr[0x100];
844 } immap_t; argument
847 typedef struct immap { argument
848 sysconf83xx_t sysconf; /* System configuration */
849 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
850 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
851 rtclk83xx_t pit; /* Periodic Interval Timer */
852 gtm83xx_t gtm[2]; /* Global Timers Module */
853 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
854 arbiter83xx_t arbiter; /* System Arbiter Registers */
855 reset83xx_t reset; /* Reset Module */
856 clk83xx_t clk; /* System Clock Module */
857 pmc83xx_t pmc; /* Power Management Control Module */
881 } immap_t; argument
883 typedef struct immap { argument
884 sysconf83xx_t sysconf; /* System configuration */
885 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
886 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
887 rtclk83xx_t pit; /* Periodic Interval Timer */
888 gtm83xx_t gtm[2]; /* Global Timers Module */
889 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
890 arbiter83xx_t arbiter; /* System Arbiter Registers */
891 reset83xx_t reset; /* Reset Module */
892 clk83xx_t clk; /* System Clock Module */
893 pmc83xx_t pmc; /* Power Management Control Module */
894 gpio83xx_t gpio[2]; /* General purpose I/O module */
895 u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
896 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
897 qepio83xx_t qepio; /* QE Parallel I/O ports */
898 u8 res1[0x800];
899 ddr83xx_t ddr; /* DDR Memory Controller Memory */
900 fsl_i2c_t i2c[2]; /* I2C Controllers */
901 u8 res2[0x1300];
902 duart83xx_t duart[2]; /* DUART */
903 u8 res3[0x200];
904 duart83xx_t duart1[2]; /* DUART */
905 u8 res4[0x500];
906 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
907 u8 res5[0x1000];
931 } immap_t; argument