include/asm/fsl_dma.h

16 #define FSL_DMA_MR_CS		0x00000001	/* Channel start */
17 #define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
18 #define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
19 #define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
20 #define FSL_DMA_MR_EOTIE	0x00000080	/* End-of-transfer interrupt en */
21 #define FSL_DMA_MR_PRC_MASK	0x00000c00	/* PCI read command */
22 #define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
23 #define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
24 #define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
25 #define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
26 #define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
27 #define FSL_DMA_MR_IRQS		0x00080000	/* Interrupt steer */
28 #define FSL_DMA_MR_DMSEN	0x00100000	/* Direct mode snooping en */
29 #define FSL_DMA_MR_BWC_MASK	0x00e00000	/* Bandwidth/pause ctl */
30 #define FSL_DMA_MR_DRCNT	0x0f000000	/* DMA request count */
32 #define FSL_DMA_SR_EOCDI	0x00000001	/* End-of-chain/direct interrupt */
33 #define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
34 #define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
35 #define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
50 #define FSL_DMA_MR_CS		0x00000001	/* Channel start */
51 #define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
52 #define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
53 #define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
54 #define FSL_DMA_MR_CA		0x00000008	/* Channel abort */
55 #define FSL_DMA_MR_CDSM		0x00000010
56 #define FSL_DMA_MR_XFE		0x00000020	/* Extended features en */
57 #define FSL_DMA_MR_EIE		0x00000040	/* Error interrupt en */
58 #define FSL_DMA_MR_EOLSIE	0x00000080	/* End-of-lists interrupt en */
59 #define FSL_DMA_MR_EOLNIE	0x00000100	/* End-of-links interrupt en */
60 #define FSL_DMA_MR_EOSIE	0x00000200	/* End-of-seg interrupt en */
61 #define FSL_DMA_MR_SRW		0x00000400	/* Single register write */
62 #define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
63 #define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
64 #define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
65 #define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
66 #define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
67 #define FSL_DMA_MR_EMP_EN	0x00200000	/* Ext master pause en */
68 #define FSL_DMA_MR_BWC_MASK	0x0f000000	/* Bandwidth/pause ctl */
69 #define FSL_DMA_MR_BWC_DIS	0x0f000000	/* Bandwidth/pause ctl disable */
71 #define FSL_DMA_SR_EOLSI	0x00000001	/* End-of-list interrupt */
72 #define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
73 #define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
74 #define FSL_DMA_SR_EOLNI	0x00000008	/* End-of-links interrupt */
75 #define FSL_DMA_SR_PE		0x00000010	/* Programming error */
76 #define FSL_DMA_SR_CH		0x00000020	/* Channel halted */
77 #define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
81 #define FSL_DMA_SATR_ESAD_MASK		0x000001ff	/* Extended source addr */
82 #define FSL_DMA_SATR_SREAD_NO_SNOOP	0x00040000	/* Read, don't snoop */
83 #define FSL_DMA_SATR_SREAD_SNOOP	0x00050000	/* Read, snoop */
84 #define FSL_DMA_SATR_SREAD_UNLOCK	0x00070000	/* Read, unlock l2 */
85 #define FSL_DMA_SATR_STRAN_MASK		0x00f00000	/* Source interface  */
86 #define FSL_DMA_SATR_SSME		0x01000000	/* Source stride en */
87 #define FSL_DMA_SATR_SPCIORDER		0x02000000	/* PCI transaction order */
88 #define FSL_DMA_SATR_STFLOWLVL_MASK	0x0c000000	/* RIO flow level */
89 #define FSL_DMA_SATR_SBPATRMU		0x20000000	/* Bypass ATMU */
92 #define FSL_DMA_DATR_EDAD_MASK		0x000001ff	/* Extended dest addr */
93 #define FSL_DMA_DATR_DWRITE_NO_SNOOP	0x00040000	/* Write, don't snoop */
94 #define FSL_DMA_DATR_DWRITE_SNOOP	0x00050000	/* Write, snoop */
95 #define FSL_DMA_DATR_DWRITE_ALLOC	0x00060000	/* Write, alloc l2 */
96 #define FSL_DMA_DATR_DWRITE_LOCK	0x00070000	/* Write, lock l2 */
97 #define FSL_DMA_DATR_DTRAN_MASK		0x00f00000	/* Dest interface  */
98 #define FSL_DMA_DATR_DSME		0x01000000	/* Dest stride en */
99 #define FSL_DMA_DATR_DPCIORDER		0x02000000	/* PCI transaction order */
100 #define FSL_DMA_DATR_DTFLOWLVL_MASK	0x0c000000	/* RIO flow level */
101 #define FSL_DMA_DATR_DBPATRMU		0x20000000	/* Bypass ATMU */