Lines Matching refs:ushort
23 #define CPM_CR_RST ((ushort)0x8000)
24 #define CPM_CR_OPCODE ((ushort)0x0f00)
25 #define CPM_CR_CHAN ((ushort)0x00f0)
26 #define CPM_CR_FLG ((ushort)0x0001)
30 #define CPM_CR_INIT_TRX ((ushort)0x0000)
31 #define CPM_CR_INIT_RX ((ushort)0x0001)
32 #define CPM_CR_INIT_TX ((ushort)0x0002)
33 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
34 #define CPM_CR_STOP_TX ((ushort)0x0004)
35 #define CPM_CR_RESTART_TX ((ushort)0x0006)
36 #define CPM_CR_SET_GADDR ((ushort)0x0008)
40 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
41 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
42 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
43 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
44 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
45 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
46 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
47 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
73 ushort cbd_sc; /* Status and Control */
74 ushort cbd_datlen; /* Data length in buffer */
78 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
79 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
80 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
81 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
82 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
83 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
84 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
85 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
86 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
87 #define BD_SC_BR ((ushort)0x0020) /* Break received */
88 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
89 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
90 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
91 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
108 ushort smc_rbase; /* Rx Buffer descriptor base address */
109 ushort smc_tbase; /* Tx Buffer descriptor base address */
112 ushort smc_mrblr; /* Max receive buffer length */
115 ushort smc_rbptr; /* Internal */
116 ushort smc_ibc; /* Internal */
120 ushort smc_tbptr; /* Internal */
121 ushort smc_tbc; /* Internal */
123 ushort smc_maxidl; /* Maximum idle characters */
124 ushort smc_tmpidl; /* Temporary idle counter */
125 ushort smc_brklen; /* Last received break length */
126 ushort smc_brkec; /* rcv'd break condition counter */
127 ushort smc_brkcr; /* xmt break count register */
128 ushort smc_rmask; /* Temporary bit mask */
130 ushort smc_rpbase; /* Relocation pointer */
139 #define SMCMR_REN ((ushort)0x0001)
140 #define SMCMR_TEN ((ushort)0x0002)
141 #define SMCMR_DM ((ushort)0x000c)
142 #define SMCMR_SM_GCI ((ushort)0x0000)
143 #define SMCMR_SM_UART ((ushort)0x0020)
144 #define SMCMR_SM_TRANS ((ushort)0x0030)
145 #define SMCMR_SM_MASK ((ushort)0x0030)
146 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
148 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
150 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
151 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
160 ushort scent_rbase;
161 ushort scent_tbase;
164 ushort scent_mrblr;
167 ushort scent_rbptr;
168 ushort scent_r_cnt;
172 ushort scent_tbptr;
173 ushort scent_t_cnt;
175 ushort scent_max_sl;
176 ushort scent_sl_cnt;
177 ushort scent_character1;
178 ushort scent_character2;
179 ushort scent_character3;
180 ushort scent_character4;
181 ushort scent_character5;
182 ushort scent_character6;
183 ushort scent_character7;
184 ushort scent_character8;
185 ushort scent_rccm;
186 ushort scent_rccr;
308 #define SCC_TODR_TOD ((ushort)0x8000)
318 ushort scc_rbase; /* Rx Buffer descriptor base address */
319 ushort scc_tbase; /* Tx Buffer descriptor base address */
322 ushort scc_mrblr; /* Max receive buffer length */
325 ushort scc_rbptr; /* Internal */
326 ushort scc_ibc; /* Internal */
330 ushort scc_tbptr; /* Internal */
331 ushort scc_tbc; /* Internal */
350 ushort sen_pads; /* Tx short frame pad character */
351 ushort sen_retlim; /* Retry limit threshold */
352 ushort sen_retcnt; /* Retry limit counter */
353 ushort sen_maxflr; /* maximum frame length register */
354 ushort sen_minflr; /* minimum frame length register */
355 ushort sen_maxd1; /* maximum DMA1 length */
356 ushort sen_maxd2; /* maximum DMA2 length */
357 ushort sen_maxd; /* Rx max DMA */
358 ushort sen_dmacnt; /* Rx DMA counter */
359 ushort sen_maxb; /* Max BD byte count */
360 ushort sen_gaddr1; /* Group address filter */
361 ushort sen_gaddr2;
362 ushort sen_gaddr3;
363 ushort sen_gaddr4;
368 ushort sen_tbuf0bcnt; /* Internal */
369 ushort sen_paddrh; /* physical address (MSB) */
370 ushort sen_paddrm;
371 ushort sen_paddrl; /* physical address (LSB) */
372 ushort sen_pper; /* persistence */
373 ushort sen_rfbdptr; /* Rx first BD pointer */
374 ushort sen_tfbdptr; /* Tx first BD pointer */
375 ushort sen_tlbdptr; /* Tx last BD pointer */
380 ushort sen_tbuf1bcnt; /* Internal */
381 ushort sen_txlen; /* Tx Frame length counter */
382 ushort sen_iaddr1; /* Individual address filter */
383 ushort sen_iaddr2;
384 ushort sen_iaddr3;
385 ushort sen_iaddr4;
386 ushort sen_boffcnt; /* Backoff counter */
391 ushort sen_taddrh; /* temp address (MSB) */
392 ushort sen_taddrm;
393 ushort sen_taddrl; /* temp address (LSB) */
400 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
401 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
402 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
403 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
404 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
405 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
409 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
410 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
411 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
412 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
413 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
414 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
415 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
416 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
417 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
418 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
419 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
420 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
421 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
425 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
426 #define BD_ENET_RX_WRAP ((ushort)0x2000)
427 #define BD_ENET_RX_INTR ((ushort)0x1000)
428 #define BD_ENET_RX_LAST ((ushort)0x0800)
429 #define BD_ENET_RX_FIRST ((ushort)0x0400)
430 #define BD_ENET_RX_MISS ((ushort)0x0100)
431 #define BD_ENET_RX_LG ((ushort)0x0020)
432 #define BD_ENET_RX_NO ((ushort)0x0010)
433 #define BD_ENET_RX_SH ((ushort)0x0008)
434 #define BD_ENET_RX_CR ((ushort)0x0004)
435 #define BD_ENET_RX_OV ((ushort)0x0002)
436 #define BD_ENET_RX_CL ((ushort)0x0001)
437 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
441 #define BD_ENET_TX_READY ((ushort)0x8000)
442 #define BD_ENET_TX_PAD ((ushort)0x4000)
443 #define BD_ENET_TX_WRAP ((ushort)0x2000)
444 #define BD_ENET_TX_INTR ((ushort)0x1000)
445 #define BD_ENET_TX_LAST ((ushort)0x0800)
446 #define BD_ENET_TX_TC ((ushort)0x0400)
447 #define BD_ENET_TX_DEF ((ushort)0x0200)
448 #define BD_ENET_TX_HB ((ushort)0x0100)
449 #define BD_ENET_TX_LC ((ushort)0x0080)
450 #define BD_ENET_TX_RL ((ushort)0x0040)
451 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
452 #define BD_ENET_TX_UN ((ushort)0x0002)
453 #define BD_ENET_TX_CSL ((ushort)0x0001)
454 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
462 ushort scc_maxidl; /* Maximum idle chars */
463 ushort scc_idlc; /* temp idle counter */
464 ushort scc_brkcr; /* Break count register */
465 ushort scc_parec; /* receive parity error counter */
466 ushort scc_frmec; /* receive framing error counter */
467 ushort scc_nosec; /* receive noise counter */
468 ushort scc_brkec; /* receive break condition counter */
469 ushort scc_brkln; /* last received break length */
470 ushort scc_uaddr1; /* UART address character 1 */
471 ushort scc_uaddr2; /* UART address character 2 */
472 ushort scc_rtemp; /* Temp storage */
473 ushort scc_toseq; /* Transmit out of sequence char */
474 ushort scc_char1; /* control character 1 */
475 ushort scc_char2; /* control character 2 */
476 ushort scc_char3; /* control character 3 */
477 ushort scc_char4; /* control character 4 */
478 ushort scc_char5; /* control character 5 */
479 ushort scc_char6; /* control character 6 */
480 ushort scc_char7; /* control character 7 */
481 ushort scc_char8; /* control character 8 */
482 ushort scc_rccm; /* receive control character mask */
483 ushort scc_rccr; /* receive control character register */
484 ushort scc_rlbc; /* receive last break character */
489 #define UART_SCCM_GLR ((ushort)0x1000)
490 #define UART_SCCM_GLT ((ushort)0x0800)
491 #define UART_SCCM_AB ((ushort)0x0200)
492 #define UART_SCCM_IDL ((ushort)0x0100)
493 #define UART_SCCM_GRA ((ushort)0x0080)
494 #define UART_SCCM_BRKE ((ushort)0x0040)
495 #define UART_SCCM_BRKS ((ushort)0x0020)
496 #define UART_SCCM_CCR ((ushort)0x0008)
497 #define UART_SCCM_BSY ((ushort)0x0004)
498 #define UART_SCCM_TX ((ushort)0x0002)
499 #define UART_SCCM_RX ((ushort)0x0001)
503 #define SCU_PSMR_FLC ((ushort)0x8000)
504 #define SCU_PSMR_SL ((ushort)0x4000)
505 #define SCU_PSMR_CL ((ushort)0x3000)
506 #define SCU_PSMR_UM ((ushort)0x0c00)
507 #define SCU_PSMR_FRZ ((ushort)0x0200)
508 #define SCU_PSMR_RZS ((ushort)0x0100)
509 #define SCU_PSMR_SYN ((ushort)0x0080)
510 #define SCU_PSMR_DRT ((ushort)0x0040)
511 #define SCU_PSMR_PEN ((ushort)0x0010)
512 #define SCU_PSMR_RPM ((ushort)0x000c)
513 #define SCU_PSMR_REVP ((ushort)0x0008)
514 #define SCU_PSMR_TPM ((ushort)0x0003)
515 #define SCU_PSMR_TEVP ((ushort)0x0003)
525 #define BD_SCC_TX_LAST ((ushort)0x0800)
530 ushort iic_rbase; /* Rx Buffer descriptor base address */
531 ushort iic_tbase; /* Tx Buffer descriptor base address */
534 ushort iic_mrblr; /* Max receive buffer length */
537 ushort iic_rbptr; /* Internal */
538 ushort iic_rbc; /* Internal */
542 ushort iic_tbptr; /* Internal */
543 ushort iic_tbc; /* Internal */
546 ushort iic_rpbase; /* Relocation pointer */
547 ushort iic_res2; /* reserved */
553 ushort spi_rbase; /* Rx Buffer descriptor base address */
554 ushort spi_tbase; /* Tx Buffer descriptor base address */
557 ushort spi_mrblr; /* Max receive buffer length */
560 ushort spi_rbptr; /* Internal */
561 ushort spi_rbc; /* Internal */
565 ushort spi_tbptr; /* Internal */
566 ushort spi_tbc; /* Internal */
569 ushort spi_rpbase; /* Relocation pointer */
570 ushort spi_res2;
575 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
576 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
577 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
578 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
579 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
580 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
581 #define SPMODE_EN ((ushort)0x0100) /* Enable */
582 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
583 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
595 ushort rbase; /* Rx Buffer descriptor base address */
596 ushort tbase; /* Tx Buffer descriptor base address */
599 ushort mrblr; /* Rx buffer length */
602 ushort rbptr; /* rb BD Pointer */
603 ushort rcount; /* Rx internal byte count */
607 ushort tbptr; /* Tx BD pointer */
608 ushort tcount; /* Tx byte count */
618 ushort disfc; /* discarded frame counter */
619 ushort crcec; /* CRC error counter */
620 ushort abtsc; /* abort sequence counter */
621 ushort nmarc; /* nonmatching address rx cnt */
622 ushort retrc; /* frame retransmission cnt */
623 ushort mflr; /* maximum frame length reg */
624 ushort max_cnt; /* maximum length counter */
625 ushort rfthr; /* received frames threshold */
626 ushort rfcnt; /* received frames count */
627 ushort hmask; /* user defined frm addr mask */
628 ushort haddr1; /* user defined frm address 1 */
629 ushort haddr2; /* user defined frm address 2 */
630 ushort haddr3; /* user defined frm address 3 */
631 ushort haddr4; /* user defined frm address 4 */
632 ushort tmp; /* temp */
633 ushort tmp_mb; /* temp */
645 #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
646 #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
647 #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
648 #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
649 #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
650 #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
651 #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
652 #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
653 #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
654 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
655 #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
656 #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
657 #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
658 #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
659 #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
660 #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
661 #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
662 #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
663 #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
664 #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
665 #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
666 #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
667 #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
668 #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
669 #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
670 #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
671 #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
672 #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
673 #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)