include/asm/cpm_85xx.h

61 #define CPM_CR_INIT_TRX		((ushort)0x0000)
62 #define CPM_CR_INIT_RX		((ushort)0x0001)
63 #define CPM_CR_INIT_TX		((ushort)0x0002)
64 #define CPM_CR_HUNT_MODE	((ushort)0x0003)
65 #define CPM_CR_STOP_TX		((ushort)0x0004)
66 #define CPM_CR_RESTART_TX	((ushort)0x0006)
67 #define CPM_CR_SET_GADDR	((ushort)0x0008)
107 	ushort	cbd_sc;		/* Status and Control */
108 	ushort	cbd_datlen;	/* Data length in buffer */
112 #define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
113 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
114 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
115 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
116 #define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
117 #define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
118 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
119 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
120 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
121 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
122 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
123 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
124 #define BD_SC_CD	((ushort)0x0001)	/* ?? */
245 #define SCC_TODR_TOD		((ushort)0x8000)
255 	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
256 	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
259 	ushort	scc_mrblr;	/* Max receive buffer length */
262 	ushort	scc_rbptr;	/* Internal */
263 	ushort	scc_ibc;	/* Internal */
267 	ushort	scc_tbptr;	/* Internal */
268 	ushort	scc_tbc;	/* Internal */
283 	ushort	sen_pads;	/* Tx short frame pad character */
284 	ushort	sen_retlim;	/* Retry limit threshold */
285 	ushort	sen_retcnt;	/* Retry limit counter */
286 	ushort	sen_maxflr;	/* maximum frame length register */
287 	ushort	sen_minflr;	/* minimum frame length register */
288 	ushort	sen_maxd1;	/* maximum DMA1 length */
289 	ushort	sen_maxd2;	/* maximum DMA2 length */
290 	ushort	sen_maxd;	/* Rx max DMA */
291 	ushort	sen_dmacnt;	/* Rx DMA counter */
292 	ushort	sen_maxb;	/* Max BD byte count */
293 	ushort	sen_gaddr1;	/* Group address filter */
294 	ushort	sen_gaddr2;
295 	ushort	sen_gaddr3;
296 	ushort	sen_gaddr4;
301 	ushort	sen_tbuf0bcnt;	/* Internal */
302 	ushort	sen_paddrh;	/* physical address (MSB) */
303 	ushort	sen_paddrm;
304 	ushort	sen_paddrl;	/* physical address (LSB) */
305 	ushort	sen_pper;	/* persistence */
306 	ushort	sen_rfbdptr;	/* Rx first BD pointer */
307 	ushort	sen_tfbdptr;	/* Tx first BD pointer */
308 	ushort	sen_tlbdptr;	/* Tx last BD pointer */
313 	ushort	sen_tbuf1bcnt;	/* Internal */
314 	ushort	sen_txlen;	/* Tx Frame length counter */
315 	ushort	sen_iaddr1;	/* Individual address filter */
316 	ushort	sen_iaddr2;
317 	ushort	sen_iaddr3;
318 	ushort	sen_iaddr4;
319 	ushort	sen_boffcnt;	/* Backoff counter */
324 	ushort	sen_taddrh;	/* temp address (MSB) */
325 	ushort	sen_taddrm;
326 	ushort	sen_taddrl;	/* temp address (LSB) */
332 #define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
333 #define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
334 #define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
335 #define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
336 #define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
337 #define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
341 #define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
342 #define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
343 #define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
344 #define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
345 #define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
346 #define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
347 #define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
348 #define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
349 #define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
350 #define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
351 #define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
352 #define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
353 #define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
358 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
359 #define BD_ENET_RX_WRAP		((ushort)0x2000)
360 #define BD_ENET_RX_INTR		((ushort)0x1000)
361 #define BD_ENET_RX_LAST		((ushort)0x0800)
362 #define BD_ENET_RX_FIRST	((ushort)0x0400)
363 #define BD_ENET_RX_MISS		((ushort)0x0100)
364 #define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
365 #define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
366 #define BD_ENET_RX_LG		((ushort)0x0020)
367 #define BD_ENET_RX_NO		((ushort)0x0010)
368 #define BD_ENET_RX_SH		((ushort)0x0008)
369 #define BD_ENET_RX_CR		((ushort)0x0004)
370 #define BD_ENET_RX_OV		((ushort)0x0002)
371 #define BD_ENET_RX_CL		((ushort)0x0001)
372 #define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
377 #define BD_ENET_TX_READY	((ushort)0x8000)
378 #define BD_ENET_TX_PAD		((ushort)0x4000)
379 #define BD_ENET_TX_WRAP		((ushort)0x2000)
380 #define BD_ENET_TX_INTR		((ushort)0x1000)
381 #define BD_ENET_TX_LAST		((ushort)0x0800)
382 #define BD_ENET_TX_TC		((ushort)0x0400)
383 #define BD_ENET_TX_DEF		((ushort)0x0200)
384 #define BD_ENET_TX_HB		((ushort)0x0100)
385 #define BD_ENET_TX_LC		((ushort)0x0080)
386 #define BD_ENET_TX_RL		((ushort)0x0040)
387 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
388 #define BD_ENET_TX_UN		((ushort)0x0002)
389 #define BD_ENET_TX_CSL		((ushort)0x0001)
390 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
398 	ushort	scc_maxidl;	/* Maximum idle chars */
399 	ushort	scc_idlc;	/* temp idle counter */
400 	ushort	scc_brkcr;	/* Break count register */
401 	ushort	scc_parec;	/* receive parity error counter */
402 	ushort	scc_frmec;	/* receive framing error counter */
403 	ushort	scc_nosec;	/* receive noise counter */
404 	ushort	scc_brkec;	/* receive break condition counter */
405 	ushort	scc_brkln;	/* last received break length */
406 	ushort	scc_uaddr1;	/* UART address character 1 */
407 	ushort	scc_uaddr2;	/* UART address character 2 */
408 	ushort	scc_rtemp;	/* Temp storage */
409 	ushort	scc_toseq;	/* Transmit out of sequence char */
410 	ushort	scc_char1;	/* control character 1 */
411 	ushort	scc_char2;	/* control character 2 */
412 	ushort	scc_char3;	/* control character 3 */
413 	ushort	scc_char4;	/* control character 4 */
414 	ushort	scc_char5;	/* control character 5 */
415 	ushort	scc_char6;	/* control character 6 */
416 	ushort	scc_char7;	/* control character 7 */
417 	ushort	scc_char8;	/* control character 8 */
418 	ushort	scc_rccm;	/* receive control character mask */
419 	ushort	scc_rccr;	/* receive control character register */
420 	ushort	scc_rlbc;	/* receive last break character */
425 #define UART_SCCM_GLR		((ushort)0x1000)
426 #define UART_SCCM_GLT		((ushort)0x0800)
427 #define UART_SCCM_AB		((ushort)0x0200)
428 #define UART_SCCM_IDL		((ushort)0x0100)
429 #define UART_SCCM_GRA		((ushort)0x0080)
430 #define UART_SCCM_BRKE		((ushort)0x0040)
431 #define UART_SCCM_BRKS		((ushort)0x0020)
432 #define UART_SCCM_CCR		((ushort)0x0008)
433 #define UART_SCCM_BSY		((ushort)0x0004)
434 #define UART_SCCM_TX		((ushort)0x0002)
435 #define UART_SCCM_RX		((ushort)0x0001)
439 #define SCU_PSMR_FLC		((ushort)0x8000)
440 #define SCU_PSMR_SL		((ushort)0x4000)
441 #define SCU_PSMR_CL		((ushort)0x3000)
442 #define SCU_PSMR_UM		((ushort)0x0c00)
443 #define SCU_PSMR_FRZ		((ushort)0x0200)
444 #define SCU_PSMR_RZS		((ushort)0x0100)
445 #define SCU_PSMR_SYN		((ushort)0x0080)
446 #define SCU_PSMR_DRT		((ushort)0x0040)
447 #define SCU_PSMR_PEN		((ushort)0x0010)
448 #define SCU_PSMR_RPM		((ushort)0x000c)
449 #define SCU_PSMR_REVP		((ushort)0x0008)
450 #define SCU_PSMR_TPM		((ushort)0x0003)
451 #define SCU_PSMR_TEVP		((ushort)0x0003)
461 #define BD_SCC_TX_LAST		((ushort)0x0800)
498 	ushort	fcc_riptr;	/* Rx Internal temp pointer */
499 	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
500 	ushort	fcc_res1;
501 	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
504 	ushort	fcc_rbdstat;	/* RxBD status */
505 	ushort	fcc_rbdlen;	/* RxBD down counter */
509 	ushort	fcc_tbdstat;	/* TxBD status */
510 	ushort	fcc_tbdlen;	/* TxBD down counter */
531 	ushort	fen_retlim;	/* Retry limit */
532 	ushort	fen_retcnt;	/* Retry counter */
533 	ushort	fen_pper;	/* Persistence */
534 	ushort	fen_boffcnt;	/* backoff counter */
537 	ushort	fen_tfcstat;	/* out of sequence TxBD */
538 	ushort	fen_tfclen;
540 	ushort	fen_mflr;	/* Maximum frame length (1518) */
541 	ushort	fen_paddrh;	/* MAC address */
542 	ushort	fen_paddrm;
543 	ushort	fen_paddrl;
544 	ushort	fen_ibdcount;	/* Internal BD counter */
545 	ushort	fen_ibdstart;	/* Internal BD start pointer */
546 	ushort	fen_ibdend;	/* Internal BD end pointer */
547 	ushort	fen_txlen;	/* Internal Tx frame length counter */
551 	ushort	fen_minflr;	/* Minimum frame length (64) */
552 	ushort	fen_taddrh;	/* Filter transfer MAC address */
553 	ushort	fen_taddrm;
554 	ushort	fen_taddrl;
555 	ushort	fen_padptr;	/* Pointer to pad byte buffer */
556 	ushort	fen_cftype;	/* control frame type */
557 	ushort	fen_cfrange;	/* control frame range */
558 	ushort	fen_maxb;	/* maximum BD count */
559 	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
560 	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
561 	ushort	fen_maxd;	/* internal max DMA count */
562 	ushort	fen_dmacnt;	/* internal DMA counter */
578 	ushort	fen_rfthr;	/* Received frames threshold */
579 	ushort	fen_rfcnt;	/* Received frames count */
584 #define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
585 #define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
586 #define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
587 #define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
588 #define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
589 #define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
590 #define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
591 #define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
612 	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
613 	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
616 	ushort	iic_mrblr;	/* Max receive buffer length */
619 	ushort	iic_rbptr;	/* Internal */
620 	ushort	iic_rbc;	/* Internal */
624 	ushort	iic_tbptr;	/* Internal */
625 	ushort	iic_tbc;	/* Internal */
632 	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
633 	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
636 	ushort	spi_mrblr;	/* Max receive buffer length */
639 	ushort	spi_rbptr;	/* Internal */
640 	ushort	spi_rbc;	/* Internal */
644 	ushort	spi_tbptr;	/* Internal */
645 	ushort	spi_tbc;	/* Internal */
653 #define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
654 #define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
655 #define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
656 #define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
657 #define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
658 #define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
659 #define SPMODE_EN	((ushort)0x0100)	/* Enable */
660 #define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
661 #define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
668 #define BD_IIC_START	((ushort)0x0400)