Lines Matching full:cache

2  * include/asm-ppc/cache.h
9 /* bytes per L1 cache line */
23  * Use the L1 data cache line size value for the minimum DMA buffer alignment
67 #define CACHECRBA       0x80000823      /* Cache configuration register address */
68 #define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
73 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
76 /* Cache control on the MPC8xx is provided through some additional
79 #define IC_CST		560	/* Instruction cache control/status */
82 #define DC_CST		568	/* Data cache control/status */
86 /* Commands.  Only the first few are available to the instruction cache.
88 #define	IDC_ENABLE	0x02000000	/* Cache enable */
89 #define IDC_DISABLE	0x04000000	/* Cache disable */
95 #define DC_FLINE	0x0e000000	/* Flush data cache line */
103 #define IDC_ENABLED	0x80000000	/* Cache is enabled */
104 #define IDC_CERR1	0x00200000	/* Cache error 1 */
105 #define IDC_CERR2	0x00100000	/* Cache error 2 */
106 #define IDC_CERR3	0x00080000	/* Cache error 3 */
108 #define DC_DFWT		0x40000000	/* Data cache is forced write through */