cpu/mpc86xx/cpu.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
37 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;  in checkcpu()
38 	volatile ccsr_gur_t *gur = &immap->im_gur;  in checkcpu()
54 	cpu = gd->arch.cpu;  in checkcpu()
56 	puts(cpu->name);  in checkcpu()
66 	if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)  in checkcpu()
68 	debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);  in checkcpu()
75 	printf("       CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));  in checkcpu()
76 	printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));  in checkcpu()
77 	printf("       DDR:%-4s MHz (%s MT/s data rate), ",  in checkcpu()
82 		printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));  in checkcpu()
88 	puts("L1:    D-cache 32 KiB enabled\n");  in checkcpu()
89 	puts("       I-cache 32 KiB enabled\n");  in checkcpu()
109 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;  in do_reset()
110 	volatile ccsr_gur_t *gur = &immap->im_gur;  in do_reset()
112 	/* Attempt board-specific reset */  in do_reset()
116 	out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);  in do_reset()
146 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;  in watchdog_reset()
147 	volatile ccsr_wdt_t *wdt = &immap->im_wdt;  in watchdog_reset()
148 	volatile ccsr_gur_t *gur = &immap->im_gur;  in watchdog_reset()
149 	u32 tmp = gur->pordevsr;  in watchdog_reset()
152 		wdt->swsrr = 0x556c;  in watchdog_reset()
153 		wdt->swsrr = 0xaa39;  in watchdog_reset()
179  * is not defined) then we might have a situation where U-Boot will attempt
184  * single bat.  If a non-power of two size is used that is less than
185  * CONFIG_MAX_MEM_MAPPED u-boot will crash.
195 		u64 sz = (u64)dram_size - BATU_SIZE(bl);  in setup_ddr_bat()