Lines Matching +full:cpu +full:- +full:nr
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
27 * Determine if U-Boot should keep secondary cores in reset, or let them out
45 int cpu_reset(u32 nr) in cpu_reset() argument
48 out_be32(&pic->pir, 1 << nr); in cpu_reset()
50 (void)in_be32(&pic->pir); in cpu_reset()
51 out_be32(&pic->pir, 0x0); in cpu_reset()
56 int cpu_status(u32 nr) in cpu_status() argument
63 if (nr == id) { in cpu_status()
66 } else if (is_core_disabled(nr)) { in cpu_status()
69 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; in cpu_status()
70 printf("Running on cpu %d\n", id); in cpu_status()
73 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); in cpu_status()
74 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); in cpu_status()
75 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); in cpu_status()
82 int cpu_disable(u32 nr) in cpu_disable() argument
86 setbits_be32(&gur->coredisrl, 1 << nr); in cpu_disable()
91 int is_core_disabled(int nr) { in is_core_disabled() argument
93 u32 coredisrl = in_be32(&gur->coredisrl); in is_core_disabled()
95 return (coredisrl & (1 << nr)); in is_core_disabled()
98 int cpu_disable(u32 nr) in cpu_disable() argument
102 switch (nr) { in cpu_disable()
104 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); in cpu_disable()
107 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); in cpu_disable()
110 printf("Invalid cpu number for disable %d\n", nr); in cpu_disable()
117 int is_core_disabled(int nr) { in is_core_disabled() argument
119 u32 devdisr = in_be32(&gur->devdisr); in is_core_disabled()
121 switch (nr) { in is_core_disabled()
127 printf("Invalid cpu number for disable %d\n", nr); in is_core_disabled()
140 int cpu_release(u32 nr, int argc, char * const argv[]) in cpu_release() argument
142 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; in cpu_release()
148 if (nr == get_my_id()) { in cpu_release()
162 if (argv[i][0] != '-') { in cpu_release()
190 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? in determine_mp_bootpg()
191 CONFIG_MAX_MEM_MAPPED : gd->ram_size) + in determine_mp_bootpg()
192 CONFIG_SYS_SDRAM_BASE - 4096; in determine_mp_bootpg()
198 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, in determine_mp_bootpg()
199 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But in determine_mp_bootpg()
200 * the way boot page chosen in u-boot avoids hitting this erratum. So only in determine_mp_bootpg()
201 * thw workaround for 3-way interleaving is needed. in determine_mp_bootpg()
203 * To make sure boot page translation works with 3-Way DDR interleaving in determine_mp_bootpg()
221 check--; in determine_mp_bootpg()
229 check--; in determine_mp_bootpg()
266 whoami = in_be32(&pic->whoami); in plat_mp_up()
268 out_be32(&ccm->bstrl, bootpg); in plat_mp_up()
274 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); in plat_mp_up()
278 in_be32(&ccm->bstrar); in plat_mp_up()
281 out_be32(&rcpm->ctbenrl, cpu_up_mask); in plat_mp_up()
283 out_be32(&gur->brrl, mask); in plat_mp_up()
287 unsigned int i, cpu, nr_cpus = cpu_numcores(); in plat_mp_up() local
289 for_each_cpu(i, cpu, nr_cpus, mask) { in plat_mp_up()
290 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) in plat_mp_up()
291 cpu_up_mask |= (1 << cpu); in plat_mp_up()
298 timeout--; in plat_mp_up()
302 printf("CPU up timeout. CPU up mask is %x should be %x\n", in plat_mp_up()
306 out_be32(&rcpm->ctbenrl, 0); in plat_mp_up()
309 in_be32(&rcpm->ctbenrl); in plat_mp_up()
314 out_be32(&rcpm->ctbenrl, mask); in plat_mp_up()
322 * reset a processor core to put it back into U-Boot's spinloop. in plat_mp_up()
324 clrbits_be32(&ccm->bstrar, LAW_EN); in plat_mp_up()
339 whoami = in_be32(&pic->whoami); in plat_mp_up()
340 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); in plat_mp_up()
343 devdisr = in_be32(&gur->devdisr); in plat_mp_up()
348 out_be32(&gur->devdisr, devdisr); in plat_mp_up()
351 up = ((1 << cpu_numcores()) - 1); in plat_mp_up()
352 bpcr = in_be32(&ecm->eebpcr); in plat_mp_up()
354 out_be32(&ecm->eebpcr, bpcr); in plat_mp_up()
370 timeout--; in plat_mp_up()
374 printf("CPU up timeout. CPU up mask is %x should be %x\n", in plat_mp_up()
382 out_be32(&gur->devdisr, devdisr); in plat_mp_up()
385 in_be32(&gur->devdisr); in plat_mp_up()
391 out_be32(&gur->devdisr, devdisr); in plat_mp_up()
399 * reset a processor core to put it back into U-Boot's spinloop. in plat_mp_up()
401 clrbits_be32(&ecm->bptr, 0x80000000); in plat_mp_up()
428 * 8K is used for the workaround of 3-way DDR interleaving in setup_mp()
441 * Store the bootpg's cache-able half address for use by secondary in setup_mp()
442 * CPU cores to continue to boot in setup_mp()
456 if (i != -1) { in setup_mp()