Lines Matching +full:tdm +full:- +full:sync +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
69 clrbits_be32(&usb_phy->pllprg[1], in usb_single_source_clk_configure()
71 setbits_be32(&usb_phy->pllprg[1], in usb_single_source_clk_configure()
83 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); in fsl_erratum_a006261_workaround()
90 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); in fsl_erratum_a006261_workaround()
92 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); in fsl_erratum_a006261_workaround()
98 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); in fsl_erratum_a006261_workaround()
102 u32 status = in_be32(&usb_phy->status1); in fsl_erratum_a006261_workaround()
112 setbits_be32(&usb_phy->config1, in fsl_erratum_a006261_workaround()
114 setbits_be32(&usb_phy->config2, in fsl_erratum_a006261_workaround()
118 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); in fsl_erratum_a006261_workaround()
121 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); in fsl_erratum_a006261_workaround()
173 if (iopc->conf) { in config_8560_ioports()
175 if (iopc->ppar) in config_8560_ioports()
177 if (iopc->psor) in config_8560_ioports()
179 if (iopc->pdir) in config_8560_ioports()
181 if (iopc->podr) in config_8560_ioports()
183 if (iopc->pdat) in config_8560_ioports()
197 * bottom of page 35-5 warns that there might in config_8560_ioports()
204 iop->ppar &= tpmsk; in config_8560_ioports()
205 iop->psor = (iop->psor & tpmsk) | psor; in config_8560_ioports()
206 iop->podr = (iop->podr & tpmsk) | podr; in config_8560_ioports()
207 iop->pdat = (iop->pdat & tpmsk) | pdat; in config_8560_ioports()
208 iop->pdir = (iop->pdir & tpmsk) | pdir; in config_8560_ioports()
209 iop->ppar |= ppar; in config_8560_ioports()
224 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { in disable_cpc_sram()
228 if (law.index == -1) { in disable_cpc_sram()
234 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); in disable_cpc_sram()
235 out_be32(&cpc->cpccsr0, 0); in disable_cpc_sram()
236 out_be32(&cpc->cpcsrcr0, 0); in disable_cpc_sram()
244 #error POST memory test cannot be enabled with TDM
254 * is not setup properly yet. Search for tdm entry in in enable_tdm_law()
259 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); in enable_tdm_law()
260 /* If tdm is defined in hwconfig, set law for tdm workaround */ in enable_tdm_law()
300 cpccfg0 = in_be32(&cpc->cpccfg0); in enable_cpc()
304 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); in enable_cpc()
307 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); in enable_cpc()
310 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); in enable_cpc()
314 setbits_be32(&cpc->cpchdbcr0, in enable_cpc()
319 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); in enable_cpc()
320 /* Read back to sync write */ in enable_cpc()
321 in_be32(&cpc->cpccsr0); in enable_cpc()
336 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) in invalidate_cpc()
339 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); in invalidate_cpc()
340 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) in invalidate_cpc()
364 u32 whoami = in_be32(&pic->whoami); in corenet_tb_init()
367 out_be32(&rcpm->ctbenrl, (1 << whoami)); in corenet_tb_init()
393 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> in fsl_erratum_a007212_workaround()
399 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> in fsl_erratum_a007212_workaround()
456 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); in cpu_init_f()
465 if (law.index != -1) in cpu_init_f()
501 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); in cpu_init_f()
502 in_be32(&gur->dcsrcr); in cpu_init_f()
534 cluster = in_be32(&gur->tp_cluster[i].lower); in enable_cluster_l2()
547 cluster = in_be32(&gur->tp_cluster[i].lower); in enable_cluster_l2()
552 u32 type = in_be32(&gur->tp_ityp[idx]); in enable_cluster_l2()
561 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); in enable_cluster_l2()
565 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); in enable_cluster_l2()
566 while ((in_be32(&l2cache->l2csr0) in enable_cluster_l2()
569 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); in enable_cluster_l2()
600 cache_ctl = l2cache->l2ctl; in l2cache_init()
604 /* Clear L2 SRAM memory-mapped base address */ in l2cache_init()
605 out_be32(&l2cache->l2srbar0, 0x0); in l2cache_init()
606 out_be32(&l2cache->l2srbar1, 0x0); in l2cache_init()
609 clrbits_be32(&l2cache->l2errdis, in l2cache_init()
614 clrbits_be32(&l2cache->l2ctl, in l2cache_init()
625 return -1; in l2cache_init()
657 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { in l2cache_init()
660 u32 l2srbar = l2cache->l2srbar0; in l2cache_init()
661 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE in l2cache_init()
664 l2cache->l2srbar0 = l2srbar; in l2cache_init()
671 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ in l2cache_init()
704 if (l2cache->l2csr0 & L2CSR0_L2E) in l2cache_init()
705 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, in l2cache_init()
719 * use the same bit-encoding as the older 8555, etc, parts.
775 sync(); in cpu_init_r()
782 sync(); in cpu_init_r()
787 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in cpu_init_r()
788 * in write shadow mode. Checking DCWS before setting SPR 976. in cpu_init_r()
826 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE); in cpu_init_r()
869 setbits_be32(p, 1 << (31 - 14)); in cpu_init_r()
879 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); in cpu_init_r()
880 __raw_readl(&lbc->lcrr); in cpu_init_r()
895 out_be32(&usb_phy1->usb_enable_override, in cpu_init_r()
907 out_be32(&usb_phy2->usb_enable_override, in cpu_init_r()
914 * multi-bit ECC errors which has impact on performance, so software in cpu_init_r()
920 setbits_be32(&dcfg->ecccr1, in cpu_init_r()
929 setbits_be32(&usb_phy->pllprg[1], in cpu_init_r()
937 setbits_be32(&usb_phy->port1.ctrl, in cpu_init_r()
939 setbits_be32(&usb_phy->port1.drvvbuscfg, in cpu_init_r()
941 setbits_be32(&usb_phy->port1.pwrfltcfg, in cpu_init_r()
943 setbits_be32(&usb_phy->port2.ctrl, in cpu_init_r()
945 setbits_be32(&usb_phy->port2.drvvbuscfg, in cpu_init_r()
947 setbits_be32(&usb_phy->port2.pwrfltcfg, in cpu_init_r()
986 * controller is configured in legacy mode instead of the in cpu_init_r()
987 * expected enterprise mode. Software needs to clear bit[28] in cpu_init_r()
988 * of HControl register to change to enterprise mode from in cpu_init_r()
989 * legacy mode. We assume that the controller is offline. in cpu_init_r()
998 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); in cpu_init_r()
1002 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); in cpu_init_r()