221 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;  in disable_cpc_sram()  local
223 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {  in disable_cpc_sram()
224 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {  in disable_cpc_sram()
234 			clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);  in disable_cpc_sram()
235 			out_be32(&cpc->cpccsr0, 0);  in disable_cpc_sram()
236 			out_be32(&cpc->cpcsrcr0, 0);  in disable_cpc_sram()
278 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;  in enable_cpc()  local
293 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {  in enable_cpc()
295 			sprintf(cpc_subarg, "cpc%u", i + 1);  in enable_cpc()
300 		cpccfg0 = in_be32(&cpc->cpccfg0);  in enable_cpc()
304 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);  in enable_cpc()
307 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);  in enable_cpc()
310 		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));  in enable_cpc()
314 			setbits_be32(&cpc->cpchdbcr0,  in enable_cpc()
319 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);  in enable_cpc()
321 		in_be32(&cpc->cpccsr0);  in enable_cpc()
332 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;  in invalidate_cpc()  local
334 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {  in invalidate_cpc()
335 		/* skip CPC when it used as all SRAM */  in invalidate_cpc()
336 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)  in invalidate_cpc()
338 		/* Flash invalidate the CPC and clear all the locks */  in invalidate_cpc()
339 		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);  in invalidate_cpc()
340 		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))  in invalidate_cpc()
496 	/* Invalidate the CPC before DDR gets enabled */  in cpu_init_f()