Lines Matching +full:de +full:- +full:asserting
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) in checkcpu()
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) in checkcpu()
90 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || in checkcpu()
92 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); in checkcpu()
93 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); in checkcpu()
102 setbits_be32(&rcpm->pcph20setr, 0xf0); in checkcpu()
105 setbits_be32(&rcpm->clpcl10setr, 1 << 1); in checkcpu()
115 printf("CPU%d: ", pic->whoami); in checkcpu()
120 cpu = gd->arch.cpu; in checkcpu()
122 puts(cpu->name); in checkcpu()
171 printf("CPU%d:%-4s MHz, ", core, in checkcpu()
179 printf("DSP CPU%d:%-4s MHz, ", j, in checkcpu()
184 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); in checkcpu()
189 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
194 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
202 printf(" DDR:%-4s MHz (%s MT/s data rate), ", in checkcpu()
207 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
213 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
223 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); in checkcpu()
231 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); in checkcpu()
239 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); in checkcpu()
244 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); in checkcpu()
249 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); in checkcpu()
250 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); in checkcpu()
251 printf("MAPLE-eTVPE:%-4s MHz\n", in checkcpu()
270 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); in checkcpu()
277 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { in checkcpu()
278 u32 rcw = in_be32(&gur->rcwsr[i]); in checkcpu()
291 /* ------------------------------------------------------------------------- */
302 * Make sure MSR[DE] = 1. This only resets the core. in do_reset()
314 /* Attempt board-specific reset */ in do_reset()
317 /* Next try asserting HRESET_REQ */ in do_reset()
318 out_be32(&gur->rstcr, 0x2); in do_reset()
336 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; in get_tbclk()
370 * Initializes on-chip MMC controllers.
400 /* Common ddr init for non-corenet fsl 85xx platforms */
408 gd->ram_size = fsl_ddr_sdram_size(); in dram_init()
410 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; in dram_init()
429 out_be32(&gur->ddrdllcr, 0x81000000); in dram_init()
432 while (in_be32(&gur->ddrdllcr) != 0x81000100) { in dram_init()
433 setbits_be32(&gur->devdisr, 0x00010000); in dram_init()
436 clrbits_be32(&gur->devdisr, 0x00010000); in dram_init()
465 gd->ram_size = dram_size; in dram_init()
474 /* Board-specific functions defined in each board's ddr.c */
589 if (ddr_esel != -1) { in reset_tlb()
593 return -1; in reset_tlb()
607 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); in arch_memory_test_advance()
614 test_cap = gd->ram_size; in arch_memory_test_advance()
617 if (p_addr < test_cap - 1) { in arch_memory_test_advance()
618 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); in arch_memory_test_advance()
619 if (reset_tlb(p_addr, p_size, phys_offset) == -1) in arch_memory_test_advance()
620 return -1; in arch_memory_test_advance()
623 printf("Testing 0x%08llx - 0x%08llx\n", in arch_memory_test_advance()
625 (u64)(*vstart) + (*phys_offset) + (*size) - 1); in arch_memory_test_advance()
635 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); in arch_memory_test_prepare()
644 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { in arch_memory_test_prepare()
650 printf("Testing 0x%08llx - 0x%08llx\n", in arch_memory_test_prepare()
652 (u64)(*vstart) + (*phys_offset) + (*size) - 1); in arch_memory_test_prepare()
670 if (ddr_esel != -1) { in arch_memory_test_cleanup()
678 setup_ddr_tlbs(gd->ram_size>>20); in arch_memory_test_cleanup()