Lines Matching +full:0 +full:x2e00
71 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
77 .fill 8,1,(((w)>>24)&0xff); \
78 .fill 8,1,(((w)>>16)&0xff); \
79 .fill 8,1,(((w)>> 8)&0xff); \
80 .fill 8,1,(((w) )&0xff)
89 .long 0x27051956 /* U-Boot Magic Number */
93 .ascii U_BOOT_VERSION_STRING, "\0"
120 lfd 1, 0(r4)
121 stfd 1, 0(r3)
126 lfd 1, 0(r3)
127 stfd 1, 0(r4)
139 * vector at offset 0x100 relative to the base set by MSR[IP]. If
140 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
141 * base address is 0xfff00000. In the case of a Power On Reset or Hard
163 _start: /* time t 0 */
180 lwz r6, 0(r7) /* Arbitrary external load */
195 1: lwz r6, 0x50b0(r3)
229 * 2) need to have an IBAT for the 0xf region,
259 li r0, 0
262 stb r0, 0(r4)
278 li r0, 0 /* Make room for stack frame header and */
301 li r3, 0 /* clear boot_flag for calling board_init_f */
315 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
318 STD_EXCEPTION(0x300, DataStorage, UnknownException)
321 STD_EXCEPTION(0x400, InstStorage, UnknownException)
325 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
329 . = 0x600
340 . = 0x700
347 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
352 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
354 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
355 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
356 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
357 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
359 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
360 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
362 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
363 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
364 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
366 . = 0x1300
386 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
388 STD_EXCEPTION(0x1400, SMI, UnknownException)
390 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
391 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
392 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
393 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
394 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
395 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
396 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
397 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
398 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
399 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
400 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
401 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
402 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
403 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
404 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
405 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
406 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
407 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
408 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
409 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
410 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
411 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
412 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
413 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
414 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
415 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
416 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
422 . = 0x3000
440 andi. r24,r23,0x3f00 /* get vector offset */
442 li r22,0
444 lwz r24,0(r23) /* virtual address of handler */
454 li r4,0
467 mtcrf 0xFF,r0
494 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
496 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
514 li r4, 0x556C
516 li r4, -0x55C7
524 andi. r4, r4, 0x4
537 lwz r4, 0x0808(r3)
538 rlwinm r0, r4, 0, ~AER_AO
539 stw r0, 0x0808(r3)
569 addis r0, r0, 0x0000
571 /* IBAT 0 */
579 /* DBAT 0 */
717 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
718 * incrementing by 0x1000 each time. The code below is sort of
722 lis r3, 0
727 addi r3, r3, 0x1000
728 cmp 0, 0, r3, r5
755 lis r4, 0
802 lis r3, 0
804 1: cmp 0, 1, r3, r5
806 lwz r5, 0(r3)
808 addi r3, r3, 0x4
862 beq 7f /* Protect against 0 count */
888 30: li r3, 0
902 4: cmpwi r6,0
908 5: dcbst 0,r4
914 6: icbi 0,r4
932 * Relocation Function, r12 point to got2+0x8000
934 * Adjust got2 pointers, no need to check for 0, this code
944 cmpwi r0,0
947 stw r0,0(r3)
957 cmpwi r0,0
963 cmpwi r0,0
965 stw r4,0(r3)
967 stw r0,0(r4)
979 cmplw 0, r3, r4
982 li r0, 0
984 stw r0, 0(r3)
986 cmplw 0, r3, r4
1008 li r9, 0x100 /* reset vector always at 0x100 */
1010 cmplw 0, r7, r8
1013 lwz r0, 0(r7)
1014 stw r0, 0(r9)
1017 cmplw 0, r7, r8
1027 addi r7, r7, 0x100 /* next exception vector */
1028 cmplw 0, r7, r8
1041 addi r7, r7, 0x100 /* next exception vector */
1042 cmplw 0, r7, r8
1049 addi r7, r7, 0x100 /* next exception vector */
1050 cmplw 0, r7, r8
1124 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1126 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1128 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1129 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1130 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1131 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1132 * 0xFF800. From the hard resetting to here, the processor fetched and
1139 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1140 * address for boot ROM, such as 0xFE000000. In this case, the default
1141 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1148 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1149 lis r4, (0x80000012)@h
1150 ori r4, r4, (0x80000012)@l
1159 twi 0,r4,0
1165 * window 0 and bank 0 correctly at here.
1170 li r5, 0x7FFF
1172 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1173 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1175 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1186 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1187 lis r4, (0x80000012)@h
1188 ori r4, r4, (0x80000012)@l
1201 twi 0,r4,0