Lines Matching full:ddr
28 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
31 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
42 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) in board_add_ram_info()
48 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) in board_add_ram_info()
127 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
158 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); in spd_sdram()
170 debug("DDR: Module mem type is %02X\n", spd.mem_type); in spd_sdram()
182 printf("DDR: The number of physical bank is %02X\n", n_ranks); in spd_sdram()
188 printf("DDR: Row number is out of range of DDRC, row=%02X\n", in spd_sdram()
195 printf("DDR: Col number is out of range of DDRC, col=%02X\n", in spd_sdram()
202 * Adjust DDR II IO voltage biasing. It just makes it work. in spd_sdram()
211 * ODT configuration recommendation from DDR Controller Chapter. in spd_sdram()
219 /* Setup DDR chip select register */ in spd_sdram()
221 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
222 ddr->cs_config[0] = ( 1 << 31 in spd_sdram()
229 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); in spd_sdram()
230 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); in spd_sdram()
233 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) in spd_sdram()
235 ddr->cs_config[1] = ( 1<<31 in spd_sdram()
241 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); in spd_sdram()
242 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); in spd_sdram()
246 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
247 ddr->cs_config[2] = ( 1 << 31 in spd_sdram()
254 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); in spd_sdram()
255 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); in spd_sdram()
258 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) in spd_sdram()
260 ddr->cs_config[3] = ( 1<<31 in spd_sdram()
266 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); in spd_sdram()
267 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); in spd_sdram()
282 * Set up LAWBAR for all of DDR. in spd_sdram()
286 debug("DDR:bar=0x%08x\n", ecm->bar); in spd_sdram()
287 debug("DDR:ar=0x%08x\n", ecm->ar); in spd_sdram()
291 * in the spd.cas_lat field. Translate it to a DDR in spd_sdram()
294 * CAS Lat DDR I DDR II Ctrl in spd_sdram()
310 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); in spd_sdram()
314 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", in spd_sdram()
318 debug("DDR: caslat SPD bit is %d\n", caslat); in spd_sdram()
324 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate); in spd_sdram()
342 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ in spd_sdram()
344 /* DDR controller clk at 350~460 */ in spd_sdram()
348 /* DDR controller clk at 280~350 */ in spd_sdram()
355 /* DDR controller clk at 230~280 */ in spd_sdram()
364 /* DDR controller clk at 90~230 */ in spd_sdram()
373 } else if (max_data_rate >= 323) { /* it is DDR 333 */ in spd_sdram()
375 /* DDR controller clk at 280~350 */ in spd_sdram()
379 /* DDR controller clk at 230~280 */ in spd_sdram()
386 /* DDR controller clk at 90~230 */ in spd_sdram()
395 } else if (max_data_rate >= 256) { /* it is DDR 266 */ in spd_sdram()
397 /* DDR controller clk at 280~350 */ in spd_sdram()
398 printf("DDR: DDR controller freq is more than " in spd_sdram()
402 /* DDR controller clk at 230~280 */ in spd_sdram()
406 /* DDR controller clk at 90~230 */ in spd_sdram()
411 } else if (max_data_rate >= 190) { /* it is DDR 200 */ in spd_sdram()
413 /* DDR controller clk at 230~350 */ in spd_sdram()
414 printf("DDR: DDR controller freq is more than " in spd_sdram()
418 /* DDR controller clk at 90~230 */ in spd_sdram()
424 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate); in spd_sdram()
425 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat); in spd_sdram()
433 ddr->debug_reg = 0x201c0000; /* CL=2 */ in spd_sdram()
435 ddr->debug_reg = 0x202c0000; /* CL=2.5 */ in spd_sdram()
437 ddr->debug_reg = 0x202c0000; /* CL=3.0 */ in spd_sdram()
441 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); in spd_sdram()
445 * Convert caslat clocks to DDR controller value. in spd_sdram()
446 * Force caslat_ctrl to be DDR Controller field-sized. in spd_sdram()
454 debug("DDR: effective data rate is %d MHz\n", effective_data_rate); in spd_sdram()
455 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", in spd_sdram()
460 * Avoid writing for DDR I. in spd_sdram()
468 ddr->timing_cfg_0 = (0 in spd_sdram()
474 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in spd_sdram()
478 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, in spd_sdram()
480 * For DDR II, they are bytes 36 and 37, in quarter nanos. in spd_sdram()
495 * DDR I: Byte 42 straight up in ns. in spd_sdram()
496 * DDR II: Byte 40 and 42 swizzled some, in ns. in spd_sdram()
523 * Convert trfc_clk to DDR controller fields. DDR I should in spd_sdram()
531 ddr->timing_cfg_1 = in spd_sdram()
544 * For DDR I, 0. in spd_sdram()
545 * For DDR II, with ODT enabled, use "a value" less than ACTTORW, in spd_sdram()
562 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. in spd_sdram()
580 * the HW will magically treat it as 1 for DDR 1. Oh Yea. in spd_sdram()
602 * Empirically set ~MCAS-to-preamble override for DDR 2. in spd_sdram()
623 ddr->timing_cfg_2 = (0 in spd_sdram()
633 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); in spd_sdram()
634 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); in spd_sdram()
642 debug("\n DDR DIMM: data bus width is 32 bit"); in spd_sdram()
645 debug("\n DDR DIMM: data bus width is 64 bit"); in spd_sdram()
648 /* Is this an ECC DDR chip? */ in spd_sdram()
660 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ in spd_sdram()
663 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ in spd_sdram()
666 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ in spd_sdram()
669 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ in spd_sdram()
672 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n"); in spd_sdram()
686 ddr->sdram_mode = in spd_sdram()
699 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); in spd_sdram()
704 ddr->sdram_mode2 = 0; in spd_sdram()
705 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); in spd_sdram()
741 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; in spd_sdram()
742 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); in spd_sdram()
754 ddr->sdram_cfg2 = (0 in spd_sdram()
760 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); in spd_sdram()
764 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in spd_sdram()
766 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); in spd_sdram()
778 * sdram_cfg[0] = 1 (ddr sdram logic enable) in spd_sdram()
780 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) in spd_sdram()
781 * 010 DDR 1 SDRAM in spd_sdram()
782 * 011 DDR 2 SDRAM in spd_sdram()
792 | SDRAM_CFG_MEM_EN /* DDR enable */ in spd_sdram()
817 ddr->err_disable = ~ECC_ERROR_ENABLE; in spd_sdram()
820 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | in spd_sdram()
824 debug("DDR:err_disable=0x%08x\n", ddr->err_disable); in spd_sdram()
825 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); in spd_sdram()
836 ddr->sdram_cfg = sdram_cfg; in spd_sdram()
840 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); in spd_sdram()
881 volatile ddr83xx_t *ddr= &immap->ddr; in ddr_enable_ecc() local
895 debug("ddr init: CPU FP write method\n"); in ddr_enable_ecc()
907 debug("ddr init duration: %ld ms\n", t_end - t_start); in ddr_enable_ecc()
910 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME) in ddr_enable_ecc()
911 ddr->err_detect |= ECC_ERROR_DETECT_MME; in ddr_enable_ecc()
912 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE) in ddr_enable_ecc()
913 ddr->err_detect |= ECC_ERROR_DETECT_MBE; in ddr_enable_ecc()
914 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE) in ddr_enable_ecc()
915 ddr->err_detect |= ECC_ERROR_DETECT_SBE; in ddr_enable_ecc()
916 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE) in ddr_enable_ecc()
917 ddr->err_detect |= ECC_ERROR_DETECT_MSE; in ddr_enable_ecc()
920 ddr->err_int_en &= ECC_ERR_INT_DISABLE; in ddr_enable_ecc()
923 ddr->err_disable &= ECC_ERROR_ENABLE; in ddr_enable_ecc()