Lines Matching +full:tdm +full:- +full:sync +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
12 #include <usb/ehci-ci.h>
57 #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ in cpu_init_f()
71 #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ in cpu_init_f()
107 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ in cpu_init_f()
110 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ in cpu_init_f()
113 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ in cpu_init_f()
116 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ in cpu_init_f()
119 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ in cpu_init_f()
122 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ in cpu_init_f()
125 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ in cpu_init_f()
134 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ in cpu_init_f()
137 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ in cpu_init_f()
140 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ in cpu_init_f()
145 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ in cpu_init_f()
148 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ in cpu_init_f()
151 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ in cpu_init_f()
154 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ in cpu_init_f()
157 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ in cpu_init_f()
160 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ in cpu_init_f()
163 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ in cpu_init_f()
172 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ in cpu_init_f()
175 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ in cpu_init_f()
178 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ in cpu_init_f()
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); in cpu_init_f()
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); in cpu_init_f()
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); in cpu_init_f()
217 /* RSR - Reset Status Register - clear all status (4.6.1.3) */ in cpu_init_f()
218 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
219 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
221 /* AER - Arbiter Event Register - store status */ in cpu_init_f()
222 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); in cpu_init_f()
223 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); in cpu_init_f()
226 * RMR - Reset Mode Register in cpu_init_f()
229 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr); in cpu_init_f()
231 /* LCRR - Clock Ratio Register (10.3.1.16) in cpu_init_f()
234 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val); in cpu_init_f()
235 __raw_readl(&im->im_lbc.lcrr); in cpu_init_f()
239 setbits_be32(&im->sysconf.spcr, SPCR_TBEN); in cpu_init_f()
245 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, in cpu_init_f()
246 &im->sysconf.sicrh); in cpu_init_f()
248 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); in cpu_init_f()
252 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); in cpu_init_f()
255 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); in cpu_init_f()
258 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); in cpu_init_f()
261 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); in cpu_init_f()
273 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; in cpu_init_f()
274 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM; in cpu_init_f()
280 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; in cpu_init_f()
281 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM; in cpu_init_f()
284 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; in cpu_init_f()
285 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM; in cpu_init_f()
288 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; in cpu_init_f()
289 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM; in cpu_init_f()
292 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; in cpu_init_f()
293 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM; in cpu_init_f()
296 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM; in cpu_init_f()
297 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM; in cpu_init_f()
300 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM; in cpu_init_f()
301 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM; in cpu_init_f()
304 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM; in cpu_init_f()
305 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM; in cpu_init_f()
308 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT; in cpu_init_f()
309 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR; in cpu_init_f()
312 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; in cpu_init_f()
313 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; in cpu_init_f()
320 setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); in cpu_init_f()
324 temp = __raw_readl(&ehci->control); in cpu_init_f()
389 "TDM-DMAC" in print_83xx_arb_event()
392 "Address-only, Clean Block", in print_83xx_arb_event()
393 "Address-only, lwarx reservation set", in print_83xx_arb_event()
394 "Single-beat or Burst write", in print_83xx_arb_event()
396 "Address-only, Flush Block", in print_83xx_arb_event()
400 "Address-only, sync", in print_83xx_arb_event()
401 "Address-only, tlbsync", in print_83xx_arb_event()
402 "Single-beat or Burst read", in print_83xx_arb_event()
403 "Single-beat or Burst read", in print_83xx_arb_event()
404 "Address-only, Kill Block", in print_83xx_arb_event()
405 "Address-only, icbi", in print_83xx_arb_event()
408 "Address-only, eieio", in print_83xx_arb_event()
410 "Single-beat write", in print_83xx_arb_event()
412 "ecowx - Illegal single-beat write", in print_83xx_arb_event()
416 "Address-only, TLB Invalidate", in print_83xx_arb_event()
418 "Single-beat or Burst read", in print_83xx_arb_event()
420 "eciwx - Illegal single-beat read", in print_83xx_arb_event()
426 int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) in print_83xx_arb_event()
428 int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) in print_83xx_arb_event()
430 int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) in print_83xx_arb_event()
432 int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) in print_83xx_arb_event()
434 int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) in print_83xx_arb_event()
437 if (!force && !gd->arch.arbiter_event_address) in print_83xx_arb_event()
442 gd->arch.arbiter_event_address); in print_83xx_arb_event()
449 return gd->arch.arbiter_event_address; in print_83xx_arb_event()
456 if (!force && !gd->arch.arbiter_event_address) in print_83xx_arb_event()
460 gd->arch.arbiter_event_attributes, in print_83xx_arb_event()
461 gd->arch.arbiter_event_address); in print_83xx_arb_event()
463 return gd->arch.arbiter_event_address; in print_83xx_arb_event()
488 ulong rsr = gd->arch.reset_status; in prt_83xx_rsr()