30 	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);  in main()
31 	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);  in main()
35 	OFFSET(FTAHBC020S_SLAVE_BSR_4,	ftahbc02s, s_bsr[4]);  in main()
36 	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);  in main()
37 	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);  in main()
41 	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);  in main()
45 	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);  in main()
46 	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);  in main()
47 	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);  in main()
48 	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);  in main()
49 	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);  in main()
50 	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);  in main()
51 	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);  in main()
52 	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);  in main()
56 	OFFSET(ANDES_PCU_PCS4,		andes_pcu, pcs4.parm);	/* 0x104 */  in main()
60 	OFFSET(DWCDDR21MCTL_CCR,	dwcddr21mctl, ccr);	/* 0x04 */  in main()
61 	OFFSET(DWCDDR21MCTL_DCR,	dwcddr21mctl, dcr);	/* 0x04 */  in main()
62 	OFFSET(DWCDDR21MCTL_IOCR,	dwcddr21mctl, iocr);	/* 0x08 */  in main()
63 	OFFSET(DWCDDR21MCTL_CSR,	dwcddr21mctl, csr);	/* 0x0c */  in main()
64 	OFFSET(DWCDDR21MCTL_DRR,	dwcddr21mctl, drr);	/* 0x10 */  in main()
65 	OFFSET(DWCDDR21MCTL_DLLCR0,	dwcddr21mctl, dllcr[0]); /* 0x24 */  in main()
66 	OFFSET(DWCDDR21MCTL_DLLCR1,	dwcddr21mctl, dllcr[1]); /* 0x28 */  in main()
67 	OFFSET(DWCDDR21MCTL_DLLCR2,	dwcddr21mctl, dllcr[2]); /* 0x2c */  in main()
68 	OFFSET(DWCDDR21MCTL_DLLCR3,	dwcddr21mctl, dllcr[3]); /* 0x30 */  in main()
69 	OFFSET(DWCDDR21MCTL_DLLCR4,	dwcddr21mctl, dllcr[4]); /* 0x34 */  in main()
70 	OFFSET(DWCDDR21MCTL_DLLCR5,	dwcddr21mctl, dllcr[5]); /* 0x38 */  in main()
71 	OFFSET(DWCDDR21MCTL_DLLCR6,	dwcddr21mctl, dllcr[6]); /* 0x3c */  in main()
72 	OFFSET(DWCDDR21MCTL_DLLCR7,	dwcddr21mctl, dllcr[7]); /* 0x40 */  in main()
73 	OFFSET(DWCDDR21MCTL_DLLCR8,	dwcddr21mctl, dllcr[8]); /* 0x44 */  in main()
74 	OFFSET(DWCDDR21MCTL_DLLCR9,	dwcddr21mctl, dllcr[9]); /* 0x48 */  in main()
75 	OFFSET(DWCDDR21MCTL_RSLR0,	dwcddr21mctl, rslr[0]);	/* 0x4c */  in main()
76 	OFFSET(DWCDDR21MCTL_RDGR0,	dwcddr21mctl, rdgr[0]);	/* 0x5c */  in main()
77 	OFFSET(DWCDDR21MCTL_DTAR,	dwcddr21mctl, dtar);	/* 0xa4 */  in main()
78 	OFFSET(DWCDDR21MCTL_MR,		dwcddr21mctl, mr);	/* 0x1f0 */  in main()