Lines Matching full:t1
71 li t1, DELAY_USEC(1000000)
77 subu t1, t1, 1
78 bgtz t1, 1b
88 lw t1, 0(t0)
90 and t1, t1, t2
91 ori t1, t1, 0xc
92 sw t1, 0(t0)
121 li t1, 0x1
123 sub t0, t0, t1
209 lw t1, 0x10(s0)
210 andi t1, t1, 0x1
211 beqz t1, MT7628_AN_DDR2_PAD
257 li t1, DDR_CFG1_REG
258 lw t0, 0(t1)
270 li t1, DDR_CFG2_REG
271 lw t0, 0(t1)
278 sw t0, 0(t1)
281 li t1, DDR_CFG3_REG
282 lw t2, 0(t1)
287 lw t1, 0(t0)
289 and t1, t1, t2
290 ori t1, t1, DDR_CFG4_SIZE_VAL
291 sw t1, 0(t0)
314 lw t1, 0x14(s1)
316 and t1, 0xff000000
317 or t1, 0x01
318 sw t1, 0x14(s1)
320 lw t1, 0x10(s1)
322 or t1, 0x10
323 sw t1, 0x10(s1)