334 static inline void set_dly(u32 bytelane, u32 dly)  in set_dly()  argument
336 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));  in set_dly()
340 	writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));  in set_dly()
343 static inline bool incr_dly(u32 bytelane)  in incr_dly()  argument
345 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));  in incr_dly()
348 		writel(r + 1, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));  in incr_dly()
368 static inline void center_dly(u32 bytelane, u32 start)  in center_dly()  argument
370 	register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)) - start;  in center_dly()
372 	writel(start + (r >> 1), BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));  in center_dly()
498 static inline int look_for(u32 bytelane)  in look_for()  argument
511 		byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane +  in look_for()
529 			if (!incr_dly(bytelane))  in look_for()
538 static inline int look_past(u32 bytelane)  in look_past()  argument
550 		byte = __raw_readb((void __iomem *)MSCC_DDR_TO + bytelane +  in look_past()
571 	if (!incr_dly(bytelane))  in look_past()
577 static inline int hal_vcoreiii_train_bytelane(u32 bytelane)  in hal_vcoreiii_train_bytelane()  argument
582 	set_dly(bytelane, 0);	/* Start training at DQS=0 */  in hal_vcoreiii_train_bytelane()
583 	while ((res = look_for(bytelane)) == DDR_TRAIN_CONTINUE)  in hal_vcoreiii_train_bytelane()
588 	dqs_s = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));  in hal_vcoreiii_train_bytelane()
589 	while ((res = look_past(bytelane)) == DDR_TRAIN_CONTINUE)  in hal_vcoreiii_train_bytelane()
596 	center_dly(bytelane, dqs_s);  in hal_vcoreiii_train_bytelane()
691 static inline int hal_vcoreiii_train_bytelane(u32 bytelane)  in hal_vcoreiii_train_bytelane()  argument
695 	set_dly(bytelane, 0);	/* Start training at DQS=0 */  in hal_vcoreiii_train_bytelane()
701 	set_dly(bytelane, 0);	/* Start training at DQS=0 */  in hal_vcoreiii_train_bytelane()