1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
21     (((0x3 & (cpudiv - 1)) << 5)  | \
22     ((0x3 & (ddrdiv - 1)) << 10) | \
23     ((0x3 & (ahbdiv - 1)) << 15) )
25 #define SET_FIELD(name, v)      (((v) & QCA953X_##name##_MASK) << \  argument
28 #define DPLL2_KI(v)             SET_FIELD(SRIF_DPLL2_KI, v)  argument
29 #define DPLL2_KD(v)             SET_FIELD(SRIF_DPLL2_KD, v)  argument
33 #define PLL_CPU_NFRAC(v)        SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)  argument
34 #define PLL_CPU_NINT(v)         SET_FIELD(PLL_CPU_CONFIG_NINT, v)  argument
35 #define PLL_CPU_REFDIV(v)       SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)  argument
36 #define PLL_CPU_OUTDIV(v)       SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)  argument
43 #define PLL_DDR_NFRAC(v)        SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)  argument
44 #define PLL_DDR_NINT(v)         SET_FIELD(PLL_DDR_CONFIG_NINT, v)  argument
45 #define PLL_DDR_REFDIV(v)       SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)  argument
46 #define PLL_DDR_OUTDIV(v)       SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)  argument
55 #define PLL_DDR_CONF_VAL        MK_PLL_DDR_CONF(0, 15, 1, 0)
61 #define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)  argument
62 #define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)  argument
63 #define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)  argument
73 #define PLL_DDR_DIT_FRAC_MAX(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)  argument
74 #define PLL_DDR_DIT_FRAC_MIN(v)     SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)  argument
75 #define PLL_DDR_DIT_FRAC_STEP(v)    SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)  argument
76 #define PLL_DDR_DIT_UPD_CNT(v)      SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)  argument
77 #define PLL_CPU_DIT_FRAC_MAX(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)  argument
78 #define PLL_CPU_DIT_FRAC_MIN(v)     SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)  argument
79 #define PLL_CPU_DIT_FRAC_STEP(v)    SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)  argument
80 #define PLL_CPU_DIT_UPD_CNT(v)      SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)  argument
93 #define PLL_CPU_DIT_FRAC_VAL    MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
94 #define PLL_DDR_DIT_FRAC_VAL    MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)