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1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
19 #define DDR_CTRL_UPD_MRS BIT(0)
22 #define DDR_REFRESH_M 0x3ff
26 #define DDR_TRAS_S 0
27 #define DDR_TRAS_M 0x1f
29 #define DDR_TRCD_M 0xf
32 #define DDR_TRP_M 0xf
35 #define DDR_TRRD_M 0xf
38 #define DDR_TRFC_M 0x7f
41 #define DDR_TMRD_M 0xf
44 #define DDR_CAS_L_M 0x17
57 #define DDR_BURST_LEN_S 0
58 #define DDR_BURST_LEN_M 0xf
65 #define DDR_TWR_M 0xf
68 #define DDR_TRTW_M 0x1f
71 #define DDR_TRTP_M 0xf
74 #define DDR_TWTR_M 0x1f
77 #define DDR_G_OPEN_L_M 0xf
91 #define DDR_TRFC_MSB_M 0x3
93 #define DDR1_CONF3_REG_VAL 0
114 #define DDR_BURST_GE0_MAX_BL_S 0
115 #define DDR_BURST_GE0_MAX_BL_M 0xf
119 #define DDR_BURST_GE1_MAX_BL_M 0xf
123 #define DDR_BURST_PCIE_MAX_BL_M 0xf
127 #define DDR_BURST_USB_MAX_BL_M 0xf
131 #define DDR_BURST_CPU_MAX_BL_M 0xf
135 #define DDR_BURST_RD_MAX_BL_M 0xf
139 #define DDR_BURST_WR_MAX_BL_M 0xf
143 #define DDR_BURST_RWP_MASK_EN_M 0x3
158 #define DDR_BURST_WMAC_MAX_BL_S 0
159 #define DDR_BURST_WMAC_MAX_BL_M 0xf
165 #define DDR2_CONF_TWL_M 0xf
170 #define DDR2_CONF_TFAW_M 0x3f
173 #define DDR2_CONF_EN BIT(0)
179 #define DDR1_EXT_MODE_VAL 0
180 #define DDR2_EXT_MODE_VAL 0x402
181 #define DDR2_EXT_MODE_OCD_VAL 0x782
182 #define DDR1_MODE_DLL_VAL 0x133
183 #define DDR2_MODE_DLL_VAL 0x143
184 #define DDR1_MODE_VAL 0x33
185 #define DDR2_MODE_VAL 0x43
186 #define DDR1_TAP_VAL 0x20
187 #define DDR2_TAP_VAL 0x10
189 #define DDR_REG_BIST_MASK_ADDR_0 0x2c
190 #define DDR_REG_BIST_MASK_ADDR_1 0x30
191 #define DDR_REG_BIST_MASK_AHB_GE0_0 0x34
192 #define DDR_REG_BIST_COMP_AHB_GE0_0 0x38
193 #define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c
194 #define DDR_REG_BIST_COMP_AHB_GE1_0 0x40
195 #define DDR_REG_BIST_COMP_ADDR_0 0x64
196 #define DDR_REG_BIST_COMP_ADDR_1 0x68
197 #define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c
198 #define DDR_REG_BIST_COMP_AHB_GE0_1 0x70
199 #define DDR_REG_BIST_MASK_AHB_GE1_1 0x74
200 #define DDR_REG_BIST_COMP_AHB_GE1_1 0x78
201 #define DDR_REG_BIST 0x11c
202 #define DDR_REG_BIST_STATUS 0x120
205 #define DDR_BIST_COMP_CNT_M 0xff
210 #define DDR_BIST_TEST_START BIT(0)
211 #define DDR_BIST_STATUS_DONE BIT(0)
214 #define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f
216 #define DDR_TAP_MAGIC_VAL 0xaa55aa55
217 #define DDR_TAP_MAX_VAL 0x40
231 /* For 16-bit DDR */ in ddr_init()
232 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
233 udelay(100); in ddr_init()
237 udelay(100); in ddr_init()
239 udelay(100); in ddr_init()
242 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); in ddr_init()
243 udelay(100); in ddr_init()
247 udelay(100); in ddr_init()
249 udelay(100); in ddr_init()
251 udelay(100); in ddr_init()
255 udelay(100); in ddr_init()
259 udelay(100); in ddr_init()
263 udelay(100); in ddr_init()
267 udelay(100); in ddr_init()
271 udelay(100); in ddr_init()
275 udelay(100); in ddr_init()
279 udelay(100); in ddr_init()
281 udelay(100); in ddr_init()
285 udelay(100); in ddr_init()
289 udelay(100); in ddr_init()
293 udelay(100); in ddr_init()
295 /* DQS 0 Tap Control */ in ddr_init()
309 /* For 16-bit DDR */ in ddr_init()
310 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
311 udelay(100); in ddr_init()
315 udelay(100); in ddr_init()
317 udelay(100); in ddr_init()
320 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); in ddr_init()
321 udelay(100); in ddr_init()
325 udelay(100); in ddr_init()
327 udelay(100); in ddr_init()
329 udelay(100); in ddr_init()
333 udelay(100); in ddr_init()
337 udelay(100); in ddr_init()
341 udelay(100); in ddr_init()
345 udelay(100); in ddr_init()
349 udelay(100); in ddr_init()
353 udelay(100); in ddr_init()
357 udelay(100); in ddr_init()
361 udelay(100); in ddr_init()
365 udelay(100); in ddr_init()
369 udelay(100); in ddr_init()
371 udelay(100); in ddr_init()
375 udelay(100); in ddr_init()
379 udelay(100); in ddr_init()
383 udelay(100); in ddr_init()
387 udelay(100); in ddr_init()
391 udelay(100); in ddr_init()
395 udelay(100); in ddr_init()
399 udelay(100); in ddr_init()
401 /* DQS 0 Tap Control */ in ddr_init()
419 last = 0; in ddr_tap_tuning()
420 cnt = 0; in ddr_tap_tuning()
421 tap = 0; in ddr_tap_tuning()
429 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1); in ddr_tap_tuning()
430 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0); in ddr_tap_tuning()
431 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1); in ddr_tap_tuning()
432 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0); in ddr_tap_tuning()
433 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1); in ddr_tap_tuning()
434 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0); in ddr_tap_tuning()
435 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1); in ddr_tap_tuning()
436 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0); in ddr_tap_tuning()
446 writel(0, regs + DDR_REG_BIST); in ddr_tap_tuning()