1 // SPDX-License-Identifier: GPL-2.0+
18 	AR934X_SDRAM = 0,
32 	[AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
33 	[AR934X_DDR1]  = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
34 	[AR934X_DDR2]  = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
51 			cycle = 0xffff;  in ar934x_ddr_init()
54 			if (gd->arch.rev) {  in ar934x_ddr_init()
55 				ctl = BIT(6);	/* Undocumented bit :-( */  in ar934x_ddr_init()
57 					cycle = 0xff;  in ar934x_ddr_init()
59 					cycle = 0xffff;  in ar934x_ddr_init()
62 				ctl = 0;  in ar934x_ddr_init()
63 				cycle = 0xffff;		/* DDR2 16bit */  in ar934x_ddr_init()
66 			writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);  in ar934x_ddr_init()
67 			udelay(100);  in ar934x_ddr_init()
69 			writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
72 			writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
80 		cycle = 0xffffffff;  in ar934x_ddr_init()
82 		writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);  in ar934x_ddr_init()
83 		udelay(100);  in ar934x_ddr_init()
86 		writel(0x13b, ddr_regs + 0x118);  in ar934x_ddr_init()
87 		udelay(100);  in ar934x_ddr_init()
92 	writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);  in ar934x_ddr_init()
93 	udelay(100);  in ar934x_ddr_init()
95 	writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);  in ar934x_ddr_init()
96 	udelay(100);  in ar934x_ddr_init()
98 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
101 	writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);  in ar934x_ddr_init()
104 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
108 		writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);  in ar934x_ddr_init()
109 		udelay(100);  in ar934x_ddr_init()
111 		writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
116 		writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);  in ar934x_ddr_init()
118 	udelay(100);  in ar934x_ddr_init()
120 	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
123 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
126 	writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);  in ar934x_ddr_init()
127 	udelay(100);  in ar934x_ddr_init()
129 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
132 	writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);  in ar934x_ddr_init()
133 	udelay(100);  in ar934x_ddr_init()
135 	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);  in ar934x_ddr_init()
136 	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);  in ar934x_ddr_init()
139 		if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {  in ar934x_ddr_init()
140 			writel(memcfg->tap,  in ar934x_ddr_init()
142 			writel(memcfg->tap,  in ar934x_ddr_init()
148 	udelay(100);  in ar934x_ddr_init()
150 	writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);  in ar934x_ddr_init()
151 	udelay(100);  in ar934x_ddr_init()
153 	writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);  in ar934x_ddr_init()
154 	udelay(100);  in ar934x_ddr_init()
156 	writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);  in ar934x_ddr_init()
157 	udelay(100);  in ar934x_ddr_init()