Lines Matching +full:li +full:-
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * Based on Atheros LSDK/QSDK and u-boot_mod project
26 (((0x3 & (cpudiv - 1)) << 5) | \
27 ((0x3 & (ddrdiv - 1)) << 10) | \
28 ((0x3 & (ahbdiv - 1)) << 15) )
33 * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
56 * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
79 li t3, 0x03
81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
87 li t2, 0xfffff7ff
91 addi t3, t3, -1
95 li t2, 0x20
99 addi t2, t2, -1
105 li t1, 0x02110E
110 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
111 li t1, 0x03
117 li t1, 0x00
122 li t1, 0x01
135 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
139 li t1, 0x19e82f01
143 li t1, 0x18e82f01
149 li t2, 0xc07fffff
151 li t2, 0x800000
157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
158 li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
166 li t1, 0x0352
170 li t1, 0x0550
180 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
184 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
190 li t2, 0x80000000
196 li t1, 0x1003E8
204 li t1, PLL_CPU_CONFIG_VAL_25M
208 li t1, PLL_CPU_CONFIG_VAL_40M
213 /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
216 li t2, 0x80000000
222 li t3, 100
223 li t4, 0
230 li t3, 5
233 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
235 li t2, 0xBFFFFFFF
240 li t2, 10
247 li t2, 0x40000000
260 li t2, 0x007FFFF8
263 li t2, 0x4000
266 addi t3, t3, -1
271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
272 li t1, PLL_CLK_CONTROL_VAL