Lines Matching refs:_ULCAST_
28 #define _ULCAST_ macro
30 #define _ULCAST_ (unsigned long) macro
115 #define ENTRYLO_G (_ULCAST_(1) << 0)
116 #define ENTRYLO_V (_ULCAST_(1) << 1)
117 #define ENTRYLO_D (_ULCAST_(1) << 2)
119 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
122 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
123 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
124 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
125 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
129 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
130 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
183 #define PG_RIE (_ULCAST_(1) << 31)
184 #define PG_XIE (_ULCAST_(1) << 30)
185 #define PG_ELPA (_ULCAST_(1) << 29)
186 #define PG_ESP (_ULCAST_(1) << 28)
187 #define PG_IEC (_ULCAST_(1) << 27)
190 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
195 #define IE_SW0 (_ULCAST_(1) << 8)
196 #define IE_SW1 (_ULCAST_(1) << 9)
197 #define IE_IRQ0 (_ULCAST_(1) << 10)
198 #define IE_IRQ1 (_ULCAST_(1) << 11)
199 #define IE_IRQ2 (_ULCAST_(1) << 12)
200 #define IE_IRQ3 (_ULCAST_(1) << 13)
201 #define IE_IRQ4 (_ULCAST_(1) << 14)
202 #define IE_IRQ5 (_ULCAST_(1) << 15)
207 #define C_SW0 (_ULCAST_(1) << 8)
208 #define C_SW1 (_ULCAST_(1) << 9)
209 #define C_IRQ0 (_ULCAST_(1) << 10)
210 #define C_IRQ1 (_ULCAST_(1) << 11)
211 #define C_IRQ2 (_ULCAST_(1) << 12)
212 #define C_IRQ3 (_ULCAST_(1) << 13)
213 #define C_IRQ4 (_ULCAST_(1) << 14)
214 #define C_IRQ5 (_ULCAST_(1) << 15)
256 #define ST0_UM (_ULCAST_(1) << 4)
257 #define ST0_IL (_ULCAST_(1) << 23)
258 #define ST0_DL (_ULCAST_(1) << 24)
270 #define STATUSF_IP0 (_ULCAST_(1) << 8)
272 #define STATUSF_IP1 (_ULCAST_(1) << 9)
274 #define STATUSF_IP2 (_ULCAST_(1) << 10)
276 #define STATUSF_IP3 (_ULCAST_(1) << 11)
278 #define STATUSF_IP4 (_ULCAST_(1) << 12)
280 #define STATUSF_IP5 (_ULCAST_(1) << 13)
282 #define STATUSF_IP6 (_ULCAST_(1) << 14)
284 #define STATUSF_IP7 (_ULCAST_(1) << 15)
286 #define STATUSF_IP8 (_ULCAST_(1) << 0)
288 #define STATUSF_IP9 (_ULCAST_(1) << 1)
290 #define STATUSF_IP10 (_ULCAST_(1) << 2)
292 #define STATUSF_IP11 (_ULCAST_(1) << 3)
294 #define STATUSF_IP12 (_ULCAST_(1) << 4)
296 #define STATUSF_IP13 (_ULCAST_(1) << 5)
298 #define STATUSF_IP14 (_ULCAST_(1) << 6)
300 #define STATUSF_IP15 (_ULCAST_(1) << 7)
301 #define ST0_IMPL (_ULCAST_(3) << 16)
320 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
322 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
324 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
332 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
334 #define CAUSEF_IP (_ULCAST_(255) << 8)
336 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
338 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
340 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
342 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
344 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
346 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
348 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
350 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
352 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
354 #define CAUSEF_IV (_ULCAST_(1) << 23)
356 #define CAUSEF_PCI (_ULCAST_(1) << 26)
358 #define CAUSEF_CE (_ULCAST_(3) << 28)
360 #define CAUSEF_TI (_ULCAST_(1) << 30)
362 #define CAUSEF_BD (_ULCAST_(1) << 31)
382 #define CONF_BE (_ULCAST_(1) << 15)
385 #define CONF_CU (_ULCAST_(1) << 3)
386 #define CONF_DB (_ULCAST_(1) << 4)
387 #define CONF_IB (_ULCAST_(1) << 5)
388 #define CONF_DC (_ULCAST_(7) << 6)
389 #define CONF_IC (_ULCAST_(7) << 9)
390 #define CONF_EB (_ULCAST_(1) << 13)
391 #define CONF_EM (_ULCAST_(1) << 14)
392 #define CONF_SM (_ULCAST_(1) << 16)
393 #define CONF_SC (_ULCAST_(1) << 17)
394 #define CONF_EW (_ULCAST_(3) << 18)
395 #define CONF_EP (_ULCAST_(15) << 24)
396 #define CONF_EC (_ULCAST_(7) << 28)
397 #define CONF_CM (_ULCAST_(1) << 31)
400 #define R4K_CONF_SW (_ULCAST_(1) << 20)
401 #define R4K_CONF_SS (_ULCAST_(1) << 21)
402 #define R4K_CONF_SB (_ULCAST_(3) << 22)
405 #define R5K_CONF_SE (_ULCAST_(1) << 12)
406 #define R5K_CONF_SS (_ULCAST_(3) << 20)
409 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
410 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
411 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
412 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
413 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
414 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
417 #define R10K_CONF_DN (_ULCAST_(3) << 3)
418 #define R10K_CONF_CT (_ULCAST_(1) << 5)
419 #define R10K_CONF_PE (_ULCAST_(1) << 6)
420 #define R10K_CONF_PM (_ULCAST_(3) << 7)
421 #define R10K_CONF_EC (_ULCAST_(15) << 9)
422 #define R10K_CONF_SB (_ULCAST_(1) << 13)
423 #define R10K_CONF_SK (_ULCAST_(1) << 14)
424 #define R10K_CONF_SS (_ULCAST_(7) << 16)
425 #define R10K_CONF_SC (_ULCAST_(7) << 19)
426 #define R10K_CONF_DC (_ULCAST_(7) << 26)
427 #define R10K_CONF_IC (_ULCAST_(7) << 29)
430 #define VR41_CONF_CS (_ULCAST_(1) << 12)
431 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
432 #define VR41_CONF_BP (_ULCAST_(1) << 16)
433 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
434 #define VR41_CONF_AD (_ULCAST_(1) << 23)
437 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
438 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
439 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
440 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
441 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
442 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
443 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
444 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
445 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
448 #define TX49_CONF_DC (_ULCAST_(1) << 16)
449 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
450 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
451 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
454 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
455 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
456 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
457 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
458 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
459 #define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16)
460 #define MIPS_CONF_M (_ULCAST_(1) << 31)
465 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
466 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
467 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
468 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
469 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
470 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
471 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
474 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
477 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
480 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
483 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
486 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
489 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
492 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
495 #define MIPS_CONF2_SA (_ULCAST_(15) << 0)
497 #define MIPS_CONF2_SL (_ULCAST_(15) << 4)
499 #define MIPS_CONF2_SS (_ULCAST_(15) << 8)
500 #define MIPS_CONF2_L2B (_ULCAST_(1) << 12)
501 #define MIPS_CONF2_SU (_ULCAST_(15) << 12)
502 #define MIPS_CONF2_TA (_ULCAST_(15) << 16)
503 #define MIPS_CONF2_TL (_ULCAST_(15) << 20)
504 #define MIPS_CONF2_TS (_ULCAST_(15) << 24)
505 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
507 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
508 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
509 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
510 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
511 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
512 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
513 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
514 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
515 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
516 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
517 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
518 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
519 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
520 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
521 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
522 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
523 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
524 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
525 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
526 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
527 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
528 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
529 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
530 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
531 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
532 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
533 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
536 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
538 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
540 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
543 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
545 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
546 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
547 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
548 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
549 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
550 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
552 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
553 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
554 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
555 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
557 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
558 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
559 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
560 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
561 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
562 #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
563 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
564 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
565 #define MIPS_CONF5_L2C (_ULCAST_(1) << 10)
566 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
567 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
568 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
569 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
571 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
573 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
577 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
579 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
581 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
582 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
589 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
590 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
594 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
600 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
602 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
604 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
606 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
608 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
609 #define MIPS_SEGCFG_USK _ULCAST_(5)
610 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
611 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
612 #define MIPS_SEGCFG_MSK _ULCAST_(2)
613 #define MIPS_SEGCFG_MK _ULCAST_(1)
614 #define MIPS_SEGCFG_UK _ULCAST_(0)
649 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
650 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
651 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
692 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
694 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
696 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
713 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
714 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
715 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
716 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
717 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
718 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
719 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
720 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
721 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
722 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
728 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
730 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
732 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
734 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
736 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
738 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
740 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
742 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
744 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
750 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
756 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
759 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
762 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
764 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
766 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
768 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
770 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
772 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
774 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
776 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
782 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
784 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
785 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1907 if ((res & _ULCAST_(1))) in tlb_read()