include/asm/mipsregs.h

66 #define CP0_DIAGNOSTIC $22
175 #define PL_4M		22
402 #define R4K_CONF_SB		(_ULCAST_(3) << 22)
438 #define R30XX_CONF_REV		(_ULCAST_(1) << 22)
487 #define MIPS_CONF1_IS_SHF	22
489 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
696 #define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
719 #define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
779  * Bits 22:20 of the FPU Status Register will be read as 0,
1249 #define read_c0_diag()		__read_32bit_c0_register($22, 0)
1250 #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
1253 #define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
1254 #define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)
1256 #define read_c0_diag1()		__read_32bit_c0_register($22, 1)
1257 #define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
1259 #define read_c0_diag2()		__read_32bit_c0_register($22, 2)
1260 #define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
1262 #define read_c0_diag3()		__read_32bit_c0_register($22, 3)
1263 #define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
1265 #define read_c0_diag4()		__read_32bit_c0_register($22, 4)
1266 #define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
1268 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
1269 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
1396 #define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
1397 #define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
1399 #define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
1400 #define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
1402 #define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
1403 #define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
1406 #define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
1407 #define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
1409 #define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
1410 #define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
1412 #define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
1413 #define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
1415 #define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
1416 #define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
1418 #define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
1419 #define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
1422 #define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
1423 #define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
1425 #define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
1426 #define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
1428 #define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
1429 #define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
1431 #define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
1432 #define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
1434 #define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
1435 #define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
1437 #define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
1438 #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)