Lines Matching +full:0 +full:x17
18 __asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr)); in mips_cache()
22 #define MIPS32_WHICH_ICACHE 0x0
23 #define MIPS32_FETCH_AND_LOCK 0x7
32 for (i = 0; i < lines; i++) { in icache_lock()
33 asm volatile (" cache %0, %1(%2)" in icache_lock()
46 #define INDEX_INVALIDATE_I 0x00
47 #define INDEX_WRITEBACK_INV_D 0x01
48 #define INDEX_LOAD_TAG_I 0x04
49 #define INDEX_LOAD_TAG_D 0x05
50 #define INDEX_STORE_TAG_I 0x08
51 #define INDEX_STORE_TAG_D 0x09
53 #define HIT_INVALIDATE_I 0x00
55 #define HIT_INVALIDATE_I 0x10
57 #define HIT_INVALIDATE_D 0x11
58 #define HIT_WRITEBACK_INV_D 0x15
63 #define CREATE_DIRTY_EXCL_D 0x0d
64 #define FILL 0x14
65 #define HIT_WRITEBACK_I 0x18
66 #define HIT_WRITEBACK_D 0x19
71 #define INDEX_INVALIDATE_SI 0x02
72 #define INDEX_WRITEBACK_INV_SD 0x03
73 #define INDEX_LOAD_TAG_SI 0x06
74 #define INDEX_LOAD_TAG_SD 0x07
75 #define INDEX_STORE_TAG_SI 0x0A
76 #define INDEX_STORE_TAG_SD 0x0B
77 #define CREATE_DIRTY_EXCL_SD 0x0f
78 #define HIT_INVALIDATE_SI 0x12
79 #define HIT_INVALIDATE_SD 0x13
80 #define HIT_WRITEBACK_INV_SD 0x17
81 #define HIT_WRITEBACK_SD 0x1b
82 #define HIT_SET_VIRTUAL_SI 0x1e
83 #define HIT_SET_VIRTUAL_SD 0x1f
88 #define R5K_PAGE_INVALIDATE_S 0x17
93 #define PAGE_INVALIDATE_T 0x16
98 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
101 #define INDEX_WRITEBACK_INV_S 0x03
102 #define INDEX_LOAD_TAG_S 0x07
103 #define INDEX_STORE_TAG_S 0x0B
104 #define HIT_INVALIDATE_S 0x13
105 #define CACHE_BARRIER 0x14
106 #define HIT_WRITEBACK_INV_S 0x17
107 #define INDEX_LOAD_DATA_I 0x18
108 #define INDEX_LOAD_DATA_D 0x19
109 #define INDEX_LOAD_DATA_S 0x1b
110 #define INDEX_STORE_DATA_I 0x1c
111 #define INDEX_STORE_DATA_D 0x1d
112 #define INDEX_STORE_DATA_S 0x1f