Lines Matching +full:0 +full:x100
13 #size-cells = <0>;
15 cpu@0 {
19 reg = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
36 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
56 ranges = <0 0x70000000 0x2000000>;
60 cpu_ctrl: syscon@0 {
62 reg = <0x0 0x2c>;
67 reg = <0x70 0x70>;
75 pinctrl-0 = <&uart_pins>;
78 reg = <0x100000 0x20>;
88 pinctrl-0 = <&uart2_pins>;
91 reg = <0x100800 0x20>;
102 #size-cells = <0>;
104 reg = <0x101000 0x40>;
106 bus-num = <0>;
116 pinctrl-0 = <&miim1_pins>;
120 reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
121 <0x1030000 0x10000>, /* VTSS_TO_REW */
122 <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
123 <0x10d0000 0x10000>, /* VTSS_TO_HSIO */
124 <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
125 <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
126 <0x1200000 0x100>, /* VTSS_TO_DEV_2 */
127 <0x1210000 0x100>, /* VTSS_TO_DEV_3 */
128 <0x1220000 0x100>, /* VTSS_TO_DEV_4 */
129 <0x1230000 0x100>, /* VTSS_TO_DEV_5 */
130 <0x1240000 0x100>, /* VTSS_TO_DEV_6 */
131 <0x1250000 0x100>, /* VTSS_TO_DEV_7 */
132 <0x1260000 0x100>, /* VTSS_TO_DEV_8 */
133 <0x1270000 0x100>, /* NA */
134 <0x1280000 0x100>, /* NA */
135 <0x1800000 0x80000>, /* VTSS_TO_QSYS */
136 <0x1880000 0x10000>; /* VTSS_TO_ANA */
147 #size-cells = <0>;
149 port0: port@0 {
150 reg = <0>;
187 #size-cells = <0>;
189 reg = <0x107009c 0x24>, <0x10700f0 0x8>;
193 phy0: ethernet-phy@0 {
194 reg = <0>;
209 reg = <0x1070008 0x4>;
214 reg = <0x1070034 0x68>;
217 gpio-ranges = <&gpio 0 0 22>;
264 pinctrl-0 = <&sgpio_pins>;
266 reg = <0x10700f8 0x100>;
269 gpio-ranges = <&sgpio 0 0 64>;