Lines Matching +full:0 +full:x28
44 * 2. Store word offset value to address 0x0
45 * 3. Load just byte from address 0x0
46 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
47 * value that's why is on address 0x0
48 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
50 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
51 lwi r7, r0, 0x28
52 swi r6, r0, 0x28 /* used first unused MB vector */
53 lbui r10, r0, 0x28 /* used first unused MB vector */
54 swi r7, r0, 0x28
57 addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
58 addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
62 swi r2, r0, 0x0 /* reset address - imm opcode */
63 swi r3, r0, 0x4 /* reset address - brai opcode */
68 rsubi r8, r10, 0x2
70 rsubi r8, r10, 0x6
76 swi r2, r0, 0x8 /* user vector exception - imm opcode */
77 swi r3, r0, 0xC /* user vector exception - brai opcode */
83 * 0x8: 0xB000XXXX
84 * 0xC: 0xB808XXXX
88 * 0xa address. Big endian use offset in r10=0 that's why is it just
89 * 0xa address. The same is done for the least significant 16 bits
90 * for 0xe address.
93 * 0x8: 0xXXXX00B0
94 * 0xC: 0xXXXX08B8
96 * Offset is for little endian setup to 0x2. rsubi instruction decrease
98 * 0x8 for the most significant 16 bits and
99 * 0xC for the least significant 16 bits
102 rsubi r8, r10, 0xa
104 rsubi r8, r10, 0xe
109 swi r2, r0, 0x10 /* interrupt - imm opcode */
110 swi r3, r0, 0x14 /* interrupt - brai opcode */
115 rsubi r8, r10, 0x12
117 rsubi r8, r10, 0x16
121 swi r2, r0, 0x20 /* hardware exception - imm opcode */
122 swi r3, r0, 0x24 /* hardware exception - brai opcode */
127 rsubi r8, r10, 0x22
129 rsubi r8, r10, 0x26
134 addik r5, r0, 0
141 ori r12, r12, 0x1a0
152 swi r0, r5, 0 /* write zero to loc */
195 andi r4, r4, 0xffff
211 andi r3, r3, 0xffff
231 addi r1, r5, 0 /* Start to use new SP */
232 addi r31, r6, 0 /* Start to use new GD */
252 addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
253 lwi r7, r0, 0x28
254 swi r6, r0, 0x28 /* used first unused MB vector */
255 lbui r10, r0, 0x28 /* used first unused MB vector */
256 swi r7, r0, 0x28
263 rsubi r8, r10, 0xa
265 rsubi r8, r10, 0xe
272 rsubi r8, r10, 0x22
274 rsubi r8, r10, 0x26
281 rsubi r8, r10, 0x12
283 rsubi r8, r10, 0x16
293 addik r22, r22, -0x10
310 addik r5, r0, 0
315 2: addi r5, r31, 0 /* gd is initialized in board_r.c */