include/asm/m5445x.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
138 #define CCM_CCR_360_PLLMULT2(x)		(((x)&0x0003))	/* 2-Bit PLL clock mode */
143 #define CCM_CCR_360_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL Clock Mode */
170 #define CCM_CCR_256_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL clock mode */
217 #define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */
218 #define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense polarity */
219 #define CCM_MISCCR_USBPUE		(0x0004)	/* USB transceiver pull-up enable */
220 #define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */
248 #define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clock divider */
251 #define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down enable */
253 #define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */
254 #define CCM_UOCSR_PWRFLT		(0x0008)	/* VBUS power fault */
257 #define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */
258 #define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */
259 #define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (read-only) */
260 #define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor enabled (read-only) */
261 #define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (read-only) */
262 #define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (read-only) */
263 #define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (read-only) */
720 #define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
722 #define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
725 #define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
729 #define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
737 #define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
751 #define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
752 #define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
788 #define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
790 #define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
791 #define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */
805 #define PCI_SCR_FC			(0x00800000)	/* Fast back-to-back */
809 #define PCI_SCR_F			(0x00000200)	/* Fast back-to-back enable */
869 #define PCI_IWCR_W0C_EN			(0x01000000)	/* Enable - Register initialize */
874 #define PCI_IWCR_W1C_EN			(0x00010000)	/* Enable - Register initialize */
879 #define PCI_IWCR_W2C_EN			(0x00000100)	/* Enable - Register initialize */