Lines Matching full:intr
42 #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
47 #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
48 #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
49 #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
50 #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
51 #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
52 #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
53 #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
54 #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
55 #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
56 #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
57 #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
58 #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
125 #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
126 #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
127 #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
128 #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
129 #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
130 #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
131 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
132 #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
133 #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
135 #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
136 #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
137 #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
138 #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */