include/asm/m5249.h

40 #define	MCFSIM_RSR		0x00	/* Reset Status reg (r/w) */
41 #define	MCFSIM_SYPCR		0x01	/* System Protection reg (r/w) */
42 #define	MCFSIM_SWIVR		0x02	/* SW Watchdog intr reg (r/w) */
43 #define	MCFSIM_SWSR		0x03	/* SW Watchdog service (r/w) */
44 #define MCFSIM_MPARK		0x0c	/* Bus master park register (r/w) */
46 #define	MCFSIM_SIMR		0x00	/* SIM Config reg (r/w) */
47 #define	MCFSIM_ICR0		0x4c	/* Intr Ctrl reg 0 (r/w) */
48 #define	MCFSIM_ICR1		0x4d	/* Intr Ctrl reg 1 (r/w) */
49 #define	MCFSIM_ICR2		0x4e	/* Intr Ctrl reg 2 (r/w) */
50 #define	MCFSIM_ICR3		0x4f	/* Intr Ctrl reg 3 (r/w) */
51 #define	MCFSIM_ICR4		0x50	/* Intr Ctrl reg 4 (r/w) */
52 #define	MCFSIM_ICR5		0x51	/* Intr Ctrl reg 5 (r/w) */
53 #define	MCFSIM_ICR6		0x52	/* Intr Ctrl reg 6 (r/w) */
54 #define	MCFSIM_ICR7		0x53	/* Intr Ctrl reg 7 (r/w) */
55 #define	MCFSIM_ICR8		0x54	/* Intr Ctrl reg 8 (r/w) */
56 #define	MCFSIM_ICR9		0x55	/* Intr Ctrl reg 9 (r/w) */
57 #define	MCFSIM_ICR10		0x56	/* Intr Ctrl reg 10 (r/w) */
58 #define	MCFSIM_ICR11		0x57	/* Intr Ctrl reg 11 (r/w) */
60 #define MCFSIM_IPR		0x40	/* Interrupt Pend reg (r/w) */
61 #define MCFSIM_IMR		0x44	/* Interrupt Mask reg (r/w) */
63 #define MCFSIM_DCR		0x100	/* DRAM Control reg (r/w) */
64 #define MCFSIM_DACR0		0x108	/* DRAM 0 Addr and Ctrl (r/w) */
65 #define MCFSIM_DMR0		0x10c	/* DRAM 0 Mask reg (r/w) */
66 #define MCFSIM_DACR1		0x110	/* DRAM 1 Addr and Ctrl (r/w) */
67 #define MCFSIM_DMR1		0x114	/* DRAM 1 Mask reg (r/w) */
77 #define MCFSIM_GPIO_OUT		0x04	/* Output register for gpio 0-31 (MBAR2) (r/w) */
78 #define MCFSIM_GPIO_EN		0x08	/* gpio 0-31 enable (r/w) */
79 #define MCFSIM_GPIO_FUNC	0x0c	/* gpio 0-31 function select (r/w) */
81 #define MCFSIM_GPIO1_OUT	0xb4	/* Output register for gpio 32-63 (MBAR2) (r/w) */
82 #define MCFSIM_GPIO1_EN		0xb8	/* gpio 32-63 enable (r/w) */
83 #define MCFSIM_GPIO1_FUNC	0xbc	/* gpio 32-63 function select (r/w) */
86 #define MCFSIM_GPIO_INT_CLEAR	0xc0	/* Secondary Interrupt status (w) */
87 #define MCFSIM_GPIO_INT_EN	0xc4	/* Secondary Interrupt status (r/w) */
90 #define MCFSIM_INT_CLEAR3	0xe0	/* 3rd Interrupt ctrl clear (w) */
91 #define MCFSIM_INT_EN3		0xe4	/* 3rd Interrupt ctrl enable (r/w) */
93 #define MCFSIM_INTLEV1		0x140	/* Interrupts 0 - 7 (r/w) */
94 #define MCFSIM_INTLEV2		0x144	/* Interrupts 8 -15 (r/w) */
95 #define MCFSIM_INTLEV3		0x148	/* Interrupts 16-23 (r/w) */
96 #define MCFSIM_INTLEV4		0x14c	/* Interrupts 24-31 (r/w) */
97 #define MCFSIM_INTLEV5		0x150	/* Interrupts 32-39 (r/w) */
98 #define MCFSIM_INTLEV6		0x154	/* Interrupts 40-47 (r/w) */
99 #define MCFSIM_INTLEV7		0x158	/* Interrupts 48-55 (r/w) */
100 #define MCFSIM_INTLEV8		0x15c	/* Interrupts 56-63 (r/w) */
102 #define MCFSIM_SPURVEC		0x167	/* Spurious Vector Register (r/w) */
103 #define MCFSIM_INTBASE		0x16b	/* Software interrupt base address (r/w) */
105 #define MCFSIM_IDECONFIG1	0x18c	/* IDE config register 1 (r/w) */
106 #define MCFSIM_IDECONFIG2	0x190	/* IDE config register 1 (r/w) */
114 #define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
117 #define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
127 #define	MCFSIM_ICR_LEVEL1	0x04	/* Level 1 intr */
136 #define	MCFSIM_ICR_PRI1		0x01	/* Priority 1 intr */