129 #define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)  argument
130 #define CCM_CIR_PRN(x)			((x) & 0x003F)  argument
157 #define CCM_CDR_USBDIV(x)		(((x)&0x0003)<<12)  argument
158 #define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clk div */  argument
159 #define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clk div */  argument
465 #define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */  argument
467 #define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */  argument
468 #define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */  argument
476 #define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */  argument
478 #define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */  argument
480 #define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */  argument
489 #define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */  argument
490 #define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */  argument
491 #define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */  argument
492 #define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */  argument
493 #define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */  argument
494 #define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge del…  argument
495 #define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge dela…  argument
498 #define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */  argument
499 #define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */  argument
500 #define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge dela…  argument
501 #define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */  argument
504 #define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */  argument
505 #define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */  argument
506 #define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)  argument
527 #define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */  argument
528 #define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for bus/flexbus clock frequency…  argument
529 #define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for SDRAM clock frequency */  argument
530 #define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */  argument
531 #define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */  argument