Lines Matching refs:u8
74 u8 resv0[0x18];
76 u8 resv1[0x6];
82 u8 rcr;
83 u8 rsr;
88 u8 ccm_resv0[0x4];
90 u8 resv1[0x2];
93 u8 resv2[0x4];
101 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
102 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
103 u8 podr_ssi; /* SSI Port Output Data Register */
104 u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
105 u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
106 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
107 u8 podr_dma; /* DMA Port Output Data Register */
108 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
109 u8 resv0[0x1];
110 u8 podr_uart; /* UART Port Output Data Register */
111 u8 podr_dspi; /* DSPI Port Output Data Register */
112 u8 podr_timer; /* Timer Port Output Data Register */
113 u8 podr_pci; /* PCI Port Output Data Register */
114 u8 podr_usb; /* USB Port Output Data Register */
115 u8 podr_atah; /* ATA High Port Output Data Register */
116 u8 podr_atal; /* ATA Low Port Output Data Register */
117 u8 podr_fec1h; /* FEC1 High Port Output Data Register */
118 u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
119 u8 resv1[0x2];
120 u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
121 u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
122 u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
123 u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
124 u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
125 u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
126 u8 pddr_ssi; /* SSI Port Data Direction Register */
127 u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
128 u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
129 u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
130 u8 pddr_dma; /* DMA Port Data Direction Register */
131 u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
132 u8 resv2[0x1];
133 u8 pddr_uart; /* UART Port Data Direction Register */
134 u8 pddr_dspi; /* DSPI Port Data Direction Register */
135 u8 pddr_timer; /* Timer Port Data Direction Register */
136 u8 pddr_pci; /* PCI Port Data Direction Register */
137 u8 pddr_usb; /* USB Port Data Direction Register */
138 u8 pddr_atah; /* ATA High Port Data Direction Register */
139 u8 pddr_atal; /* ATA Low Port Data Direction Register */
140 u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
141 u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
142 u8 resv3[0x2];
143 u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
144 u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
145 u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
146 u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
147 u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
148 u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
149 u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
150 u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
151 u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
152 u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
153 u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
154 u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
155 u8 resv4[0x1];
156 u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
157 u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
158 u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
159 u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
160 u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
161 u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
162 u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
163 u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
164 u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
165 u8 resv5[0x2];
166 u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
167 u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
168 u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
169 u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
170 u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
171 u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
172 u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
173 u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
174 u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
175 u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
176 u8 pclrr_dma; /* DMA Port Clear Output Data Register */
177 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
178 u8 resv6[0x1];
179 u8 pclrr_uart; /* UART Port Clear Output Data Register */
180 u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
181 u8 pclrr_timer; /* Timer Port Clear Output Data Register */
182 u8 pclrr_pci; /* PCI Port Clear Output Data Register */
183 u8 pclrr_usb; /* USB Port Clear Output Data Register */
184 u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
185 u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
186 u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
187 u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
188 u8 resv7[0x2];
189 u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
190 u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
191 u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
192 u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
193 u8 par_fec; /* FEC Pin Assignment Register */
194 u8 par_dma; /* DMA Pin Assignment Register */
195 u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
196 u8 par_dspi; /* DSPI Pin Assignment Register */
197 u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
198 u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
199 u8 par_timer; /* Time Pin Assignment Register */
200 u8 par_usb; /* USB Pin Assignment Register */
201 u8 resv8[0x1];
202 u8 par_uart; /* UART Pin Assignment Register */
206 u8 par_irq; /* IRQ Pin Assignment Register */
207 u8 resv9[0x1];
209 u8 mscr_sdram; /* SDRAM Mode Select Control Register */
210 u8 mscr_pci; /* PCI Mode Select Control Register */
211 u8 resv10[0x2];
212 u8 dscr_i2c; /* I2C Drive Strength Control Register */
213 u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
214 u8 dscr_fec; /* FEC Drive Strength Control Register */
215 u8 dscr_uart; /* UART Drive Strength Control Register */
216 u8 dscr_dspi; /* DSPI Drive Strength Control Register */
217 u8 dscr_timer; /* TIMER Drive Strength Control Register */
218 u8 dscr_ssi; /* SSI Drive Strength Control Register */
219 u8 dscr_dma; /* DMA Drive Strength Control Register */
220 u8 dscr_debug; /* DEBUG Drive Strength Control Register */
221 u8 dscr_reset; /* RESET Drive Strength Control Register */
222 u8 dscr_irq; /* IRQ Drive Strength Control Register */
223 u8 dscr_usb; /* USB Drive Strength Control Register */
224 u8 dscr_ata; /* ATA Drive Strength Control Register */
233 u8 resv0[0x100];
310 u8 rsvd1[19]; /* 0x00 - 0x12 */
311 u8 wcr; /* 0x13 */
314 u8 rsvd3[3]; /* 0x18 - 0x1A */
315 u8 cwsr; /* 0x1B */
316 u8 rsvd4[3]; /* 0x1C - 0x1E */
317 u8 scmisr; /* 0x1F */
319 u8 bcr; /* 0x24 */
320 u8 rsvd6[74]; /* 0x25 - 0x6F */
322 u8 rsvd7; /* 0x74 */
323 u8 cfier; /* 0x75 */
324 u8 cfloc; /* 0x76 */
325 u8 cfatr; /* 0x77 */