Lines Matching refs:u32
229 u32 sdmr; /* SDRAM Mode/Extended Mode Register */
230 u32 sdcr; /* SDRAM Control Register */
231 u32 sdcfg1; /* SDRAM Configuration Register 1 */
232 u32 sdcfg2; /* SDRAM Chip Select Register */
234 u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
235 u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
240 u32 pcr; /* PLL Control Register */
241 u32 psr; /* PLL Status Register */
245 u32 idr; /* 0x00 Device Id / Vendor Id Register */
246 u32 scr; /* 0x04 Status / command Register */
247 u32 ccrir; /* 0x08 Class Code / Revision Id Register */
248 u32 cr1; /* 0x0c Configuration 1 Register */
249 u32 bar0; /* 0x10 Base address register 0 Register */
250 u32 bar1; /* 0x14 Base address register 1 Register */
251 u32 bar2; /* 0x18 Base address register 2 Register */
252 u32 bar3; /* 0x1c Base address register 3 Register */
253 u32 bar4; /* 0x20 Base address register 4 Register */
254 u32 bar5; /* 0x24 Base address register 5 Register */
255 u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
256 u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
257 u32 erbar; /* 0x30 Expansion ROM Base Address Register */
258 u32 cpr; /* 0x34 Capabilities Pointer Register */
259 u32 rsvd1; /* 0x38 */
260 u32 cr2; /* 0x3c Configuration Register 2 */
261 u32 rsvd2[8]; /* 0x40 - 0x5f */
264 u32 gscr; /* 0x60 Global Status / Control Register */
265 u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
266 u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
267 u32 tcr1; /* 0x6c Target Control 1 Register */
268 u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
269 u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
270 u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
271 u32 rsvd3; /* 0x7c */
272 u32 iwcr; /* 0x80 Initiator Window Configuration Register */
273 u32 icr; /* 0x84 Initiator Control Register */
274 u32 isr; /* 0x88 Initiator Status Register */
275 u32 tcr2; /* 0x8c Target Control 2 Register */
276 u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
277 u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
278 u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
279 u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
280 u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
281 u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
282 u32 intr; /* 0xa8 Interrupt Register */
283 u32 rsvd4[19]; /* 0xac - 0xf7 */
284 u32 car; /* 0xf8 Configuration Address Register */
290 u32 acr; /* Arbiter Control Register */
291 u32 asr; /* Arbiter Status Register */
297 u32 mpr; /* 0x00 Master Privilege Register */
298 u32 rsvd1[7];
299 u32 pacra; /* 0x20 Peripheral Access Control Register A */
300 u32 pacrb; /* 0x24 Peripheral Access Control Register B */
301 u32 pacrc; /* 0x28 Peripheral Access Control Register C */
302 u32 pacrd; /* 0x2C Peripheral Access Control Register D */
303 u32 rsvd2[4];
304 u32 pacre; /* 0x40 Peripheral Access Control Register E */
305 u32 pacrf; /* 0x44 Peripheral Access Control Register F */
306 u32 pacrg; /* 0x48 Peripheral Access Control Register G */
318 u32 rsvd5; /* 0x20 - 0x23 */
321 u32 cfadr; /* 0x70 */
326 u32 rsvd8; /* 0x78 - 0x7B */
327 u32 cfdtr; /* 0x7C */
331 u32 rsvd1[3];
332 u32 gocu;
333 u32 gocl;