include/asm/immap_5445x.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
89 	u16 ccr;		/* Chip Configuration Register (256 TEPBGA, Read-only) */
91 	u16 rcon;		/* Reset Configuration (256 TEPBGA, Read-only) */
92 	u16 cir;		/* Chip Identification Register (Read-only) */
96 	u16 uocsr;		/* USB On-the-Go Controller Status Register */
101 	u8 podr_fec0h;		/* FEC0 High Port Output Data Register */
102 	u8 podr_fec0l;		/* FEC0 Low Port Output Data Register */
103 	u8 podr_ssi;		/* SSI Port Output Data Register */
104 	u8 podr_fbctl;		/* Flexbus Control Port Output Data Register */
105 	u8 podr_be;		/* Flexbus Byte Enable Port Output Data Register */
106 	u8 podr_cs;		/* Flexbus Chip-Select Port Output Data Register */
107 	u8 podr_dma;		/* DMA Port Output Data Register */
108 	u8 podr_feci2c;		/* FEC1 / I2C Port Output Data Register */
110 	u8 podr_uart;		/* UART Port Output Data Register */
111 	u8 podr_dspi;		/* DSPI Port Output Data Register */
112 	u8 podr_timer;		/* Timer Port Output Data Register */
113 	u8 podr_pci;		/* PCI Port Output Data Register */
114 	u8 podr_usb;		/* USB Port Output Data Register */
115 	u8 podr_atah;		/* ATA High Port Output Data Register */
116 	u8 podr_atal;		/* ATA Low Port Output Data Register */
117 	u8 podr_fec1h;		/* FEC1 High Port Output Data Register */
118 	u8 podr_fec1l;		/* FEC1 Low Port Output Data Register */
120 	u8 podr_fbadh;		/* Flexbus AD High Port Output Data Register */
121 	u8 podr_fbadmh;		/* Flexbus AD Med-High Port Output Data Register */
122 	u8 podr_fbadml;		/* Flexbus AD Med-Low Port Output Data Register */
123 	u8 podr_fbadl;		/* Flexbus AD Low Port Output Data Register */
125 	u8 pddr_fec0l;		/* FEC0 Low Port Data Direction Register */
129 	u8 pddr_cs;		/* Flexbus Chip-Select Port Data Direction Register */
139 	u8 pddr_atal;		/* ATA Low Port Data Direction Register */
141 	u8 pddr_fec1l;		/* FEC1 Low Port Data Direction Register */
144 	u8 pddr_fbadmh;		/* Flexbus AD Med-High Port Data Direction Register */
145 	u8 pddr_fbadml;		/* Flexbus AD Med-Low Port Data Direction Register */
146 	u8 pddr_fbadl;		/* Flexbus AD Low Port Data Direction Register */
148 	u8 ppdsdr_fec0l;	/* FEC0 Low Port Clear Output Data Register */
152 	u8 ppdsdr_cs;		/* Flexbus Chip-Select Port Pin Data/Set Data Register */
162 	u8 ppdsdr_atal;		/* ATA Low Port Pin Data/Set Data Register */
164 	u8 ppdsdr_fec1l;	/* FEC1 Low Port Pin Data/Set Data Register */
167 	u8 ppdsdr_fbadmh;	/* Flexbus AD Med-High Port Pin Data/Set Data Register */
168 	u8 ppdsdr_fbadml;	/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
169 	u8 ppdsdr_fbadl;	/* Flexbus AD Low Port Pin Data/Set Data Register */
170 	u8 pclrr_fec0h;		/* FEC0 High Port Clear Output Data Register */
171 	u8 pclrr_fec0l;		/* FEC0 Low Port Pin Data/Set Data Register */
172 	u8 pclrr_ssi;		/* SSI Port Clear Output Data Register */
173 	u8 pclrr_fbctl;		/* Flexbus Control Port Clear Output Data Register */
174 	u8 pclrr_be;		/* Flexbus Byte Enable Port Clear Output Data Register */
175 	u8 pclrr_cs;		/* Flexbus Chip-Select Port Clear Output Data Register */
176 	u8 pclrr_dma;		/* DMA Port Clear Output Data Register */
177 	u8 pclrr_feci2c;	/* FEC1 / I2C Port Clear Output Data Register */
179 	u8 pclrr_uart;		/* UART Port Clear Output Data Register */
180 	u8 pclrr_dspi;		/* DSPI Port Clear Output Data Register */
181 	u8 pclrr_timer;		/* Timer Port Clear Output Data Register */
182 	u8 pclrr_pci;		/* PCI Port Clear Output Data Register */
183 	u8 pclrr_usb;		/* USB Port Clear Output Data Register */
184 	u8 pclrr_atah;		/* ATA High Port Clear Output Data Register */
185 	u8 pclrr_atal;		/* ATA Low Port Clear Output Data Register */
186 	u8 pclrr_fec1h;		/* FEC1 High Port Clear Output Data Register */
187 	u8 pclrr_fec1l;		/* FEC1 Low Port Clear Output Data Register */
189 	u8 pclrr_fbadh;		/* Flexbus AD High Port Clear Output Data Register */
190 	u8 pclrr_fbadmh;	/* Flexbus AD Med-High Port Clear Output Data Register */
191 	u8 pclrr_fbadml;	/* Flexbus AD Med-Low Port Clear Output Data Register */
192 	u8 pclrr_fbadl;		/* Flexbus AD Low Port Clear Output Data Register */
197 	u8 par_be;		/* Flexbus Byte-Enable Pin Assignment Register */
198 	u8 par_cs;		/* Flexbus Chip-Select Pin Assignment Register */
261 	u32 rsvd2[8];		/* 0x40 - 0x5f */
283 	u32 rsvd4[19];		/* 0xac - 0xf7 */
310 	u8 rsvd1[19];		/* 0x00 - 0x12 */
312 	u16 rsvd2;		/* 0x14 - 0x15 */
314 	u8 rsvd3[3];		/* 0x18 - 0x1A */
316 	u8 rsvd4[3];		/* 0x1C - 0x1E */
318 	u32 rsvd5;		/* 0x20 - 0x23 */
320 	u8 rsvd6[74];		/* 0x25 - 0x6F */
326 	u32 rsvd8;		/* 0x78 - 0x7B */