Lines Matching full:clear
148 u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
170 u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
172 u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
173 u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
174 u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
175 u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
176 u8 pclrr_dma; /* DMA Port Clear Output Data Register */
177 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
179 u8 pclrr_uart; /* UART Port Clear Output Data Register */
180 u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
181 u8 pclrr_timer; /* Timer Port Clear Output Data Register */
182 u8 pclrr_pci; /* PCI Port Clear Output Data Register */
183 u8 pclrr_usb; /* USB Port Clear Output Data Register */
184 u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
185 u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
186 u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
187 u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
189 u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
190 u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
191 u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
192 u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */