Lines Matching refs:u32
69 u32 mpr0; /* 0x00 Master Privilege Register 0 */
70 u32 res1[15]; /* 0x04 - 0x3F */
71 u32 pacrh; /* 0x40 Peripheral Access Control Register H */
72 u32 res2[3]; /* 0x44 - 0x53 */
73 u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
78 u32 mpr1; /* 0x00 Master Privilege Register */
79 u32 res1[7]; /* 0x04 - 0x1F */
80 u32 pacra; /* 0x20 Peripheral Access Control Register A */
81 u32 pacrb; /* 0x24 Peripheral Access Control Register B */
82 u32 pacrc; /* 0x28 Peripheral Access Control Register C */
83 u32 pacrd; /* 0x2C Peripheral Access Control Register D */
84 u32 res2[4]; /* 0x30 - 0x3F */
85 u32 pacre; /* 0x40 Peripheral Access Control Register E */
86 u32 pacrf; /* 0x44 Peripheral Access Control Register F */
87 u32 pacrg; /* 0x48 Peripheral Access Control Register G */
88 u32 res3[2]; /* 0x4C - 0x53 */
89 u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
102 u32 res5; /* 0x20 */
103 u32 bcr; /* 0x24 Burst Configuration Register */
104 u32 res6[18]; /* 0x28 - 0x6F */
105 u32 cfadr; /* 0x70 Core Fault Address Register */
110 u32 res8; /* 0x78 */
111 u32 cfdtr; /* 0x7C Core Fault Data Register */
132 u32 res3; /* 0x08 */
318 u32 id; /* 0x000 Identification Register */
319 u32 hwgeneral; /* 0x004 General HW Parameters */
320 u32 hwhost; /* 0x008 Host HW Parameters */
321 u32 hwdev; /* 0x00C Device HW parameters */
322 u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
323 u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
324 u32 res1[58]; /* 0x18 - 0xFF */
328 u32 hcsparams; /* 0x104 Host Structural Parameters */
329 u32 hccparams; /* 0x108 Host Capability Parameters */
330 u32 res3[5]; /* 0x10C - 0x11F */
333 u32 dccparams; /* 0x124 Device Capability Parameters */
334 u32 res5[6]; /* 0x128 - 0x13F */
335 u32 cmd; /* 0x140 USB Command */
336 u32 sts; /* 0x144 USB Status */
337 u32 intr; /* 0x148 USB Interrupt Enable */
338 u32 frindex; /* 0x14C USB Frame Index */
339 u32 res6; /* 0x150 */
340 u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
341 u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
342 u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
343 u32 burstsize; /* 0x160 Master Interface Data Burst Size */
344 u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
345 u32 res7[6]; /* 0x168 - 0x17F */
346 u32 cfgflag; /* 0x180 Configure Flag Register */
347 u32 portsc1; /* 0x184 Port Status/Control */
348 u32 res8[7]; /* 0x188 - 0x1A3 */
349 u32 otgsc; /* 0x1A4 On The Go Status and Control */
350 u32 mode; /* 0x1A8 USB mode register */
351 u32 eptsetstat; /* 0x1AC Endpoint Setup status */
352 u32 eptprime; /* 0x1B0 Endpoint initialization */
353 u32 eptflush; /* 0x1B4 Endpoint de-initialize */
354 u32 eptstat; /* 0x1B8 Endpoint status */
355 u32 eptcomplete; /* 0x1BC Endpoint Complete */
356 u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
357 u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
358 u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
359 u32 eptctrl3; /* 0x1CC Endpoint control 3 */
364 u32 mode; /* 0x00 Mode/Extended Mode register */
365 u32 ctrl; /* 0x04 Control register */
366 u32 cfg1; /* 0x08 Configuration register 1 */
367 u32 cfg2; /* 0x0C Configuration register 2 */
368 u32 res1[64]; /* 0x10 - 0x10F */
369 u32 cs0; /* 0x110 Chip Select 0 Configuration */
370 u32 cs1; /* 0x114 Chip Select 1 Configuration */