Lines Matching defs:pwm_ctrl
99 typedef struct pwm_ctrl { struct
100 u8 en; /* 0x00 PWM Enable */
101 u8 pol; /* 0x01 Polarity */
102 u8 clk; /* 0x02 Clock Select */
103 u8 prclk; /* 0x03 Prescale Clock Select */
104 u8 cae; /* 0x04 Center Align Enable */
105 u8 ctl; /* 0x05 Ctrl */
106 u8 res1[2]; /* 0x06 - 0x07 */
107 u8 scla; /* 0x08 Scale A */
108 u8 sclb; /* 0x09 Scale B */
109 u8 res2[2]; /* 0x0A - 0x0B */
110 u8 cnt0; /* 0x0C Channel 0 Counter */
111 u8 cnt1; /* 0x0D Channel 1 Counter */
112 u8 cnt2; /* 0x0E Channel 2 Counter */
113 u8 cnt3; /* 0x0F Channel 3 Counter */
114 u8 cnt4; /* 0x10 Channel 4 Counter */
115 u8 cnt5; /* 0x11 Channel 5 Counter */
116 u8 cnt6; /* 0x12 Channel 6 Counter */
117 u8 cnt7; /* 0x13 Channel 7 Counter */
118 u8 per0; /* 0x14 Channel 0 Period */
119 u8 per1; /* 0x15 Channel 1 Period */
120 u8 per2; /* 0x16 Channel 2 Period */
121 u8 per3; /* 0x17 Channel 3 Period */
122 u8 per4; /* 0x18 Channel 4 Period */
123 u8 per5; /* 0x19 Channel 5 Period */
124 u8 per6; /* 0x1A Channel 6 Period */
125 u8 per7; /* 0x1B Channel 7 Period */
126 u8 dty0; /* 0x1C Channel 0 Duty */
127 u8 dty1; /* 0x1D Channel 1 Duty */
128 u8 dty2; /* 0x1E Channel 2 Duty */
129 u8 dty3; /* 0x1F Channel 3 Duty */
130 u8 dty4; /* 0x20 Channel 4 Duty */
131 u8 dty5; /* 0x21 Channel 5 Duty */
132 u8 dty6; /* 0x22 Channel 6 Duty */
133 u8 dty7; /* 0x23 Channel 7 Duty */
134 u8 sdn; /* 0x24 Shutdown */
135 u8 res3[3]; /* 0x25 - 0x27 */