cpu/mcf532x/speed.c

1 // SPDX-License-Identifier: GPL-2.0+
4  * (C) Copyright 2000-2003
7  * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
8  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
49 /* Get the value of the current system clock */
57 	if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {  in get_sys_clock()
58 		divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);  in get_sys_clock()
67 		u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;  in get_sys_clock()
68 		u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));  in get_sys_clock()
69 		u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;  in get_sys_clock()
74 		return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);  in get_sys_clock()
83  *  div     Desired system frequency divider
86  *  The resulting output system frequency
100 	temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));  in clock_limp()
102 	/* Apply the divider to the system clock */  in clock_limp()
103 	out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));  in clock_limp()
105 	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);  in clock_limp()
117 	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);  in clock_exit_limp()
120 	while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))  in clock_exit_limp()
131  *  fref    PLL reference clock frequency in KHz
132  *  fsys    Desired PLL output frequency in KHz
136  *  The resulting output system frequency
153 		u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;  in clock_pll()
154 		mfd = (in_be32(&pll->pcr) & 0x3F) + 1;  in clock_pll()
159 		mfd = in_8(&pll->pfdr);  in clock_pll()
165 	/* Check bounds of requested system clock */  in clock_pll()
182 	/* Determine the output frequency for selected values */  in clock_pll()
188 	/* Determine the output frequency for selected values */  in clock_pll()
199 	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)  in clock_pll()
200 		clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);  in clock_pll()
203 	 * Initialize the PLL to generate the new system clock frequency.  in clock_pll()
211 	out_be32(&pll->pdr,  in clock_pll()
212 		PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |  in clock_pll()
213 		PLL_PDR_OUTDIV2(BUSDIV - 1)	|  in clock_pll()
214 		PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |  in clock_pll()
215 		PLL_PDR_OUTDIV4(USBDIV - 1));  in clock_pll()
217 	clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);  in clock_pll()
218 	setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));  in clock_pll()
222 	out_8(&pll->podr,  in clock_pll()
225 	out_8(&pll->pfdr, mfd);  in clock_pll()
232 	if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)  in clock_pll()
233 		setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);  in clock_pll()
250 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
253 	gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;  in get_clocks()
254 	gd->cpu_clk = (gd->bus_clk * 3);  in get_clocks()
257 	gd->arch.i2c1_clk = gd->bus_clk;  in get_clocks()