Lines Matching +full:de +full:- +full:asserting

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (c) 2013 - 2017 Xilinx Inc.
24  * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
92 		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);  in zynq_slcr_lock()
100 		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);  in zynq_slcr_unlock()
117 	 * the FSBL not loading the bitstream after soft-reboot  in zynq_slcr_cpu_reset()
120 	clrbits_le32(&slcr_base->reboot_status, 0xF000000);  in zynq_slcr_cpu_reset()
122 	writel(1, &slcr_base->pss_rst_ctrl);  in zynq_slcr_cpu_reset()
131 	/* Disable AXI interface by asserting FPGA resets */  in zynq_slcr_devcfg_disable()
132 	writel(0xF, &slcr_base->fpga_rst_ctrl);  in zynq_slcr_devcfg_disable()
134 	/* Disable Level shifters before setting PS-PL */  in zynq_slcr_devcfg_disable()
135 	reg_val = readl(&slcr_base->lvl_shftr_en);  in zynq_slcr_devcfg_disable()
137 	writel(reg_val, &slcr_base->lvl_shftr_en);  in zynq_slcr_devcfg_disable()
140 	writel(0xA, &slcr_base->lvl_shftr_en);  in zynq_slcr_devcfg_disable()
150 	writel(0xF, &slcr_base->lvl_shftr_en);  in zynq_slcr_devcfg_enable()
152 	/* Enable AXI interface by de-asserting FPGA resets */  in zynq_slcr_devcfg_enable()
153 	writel(0x0, &slcr_base->fpga_rst_ctrl);  in zynq_slcr_devcfg_enable()
161 	return readl(&slcr_base->boot_mode);  in zynq_slcr_get_boot_mode()
166 	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>  in zynq_slcr_get_idcode()
171  * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
188 			for (j = 0; j < mio_ptr->num_pins; j++) {  in zynq_slcr_get_mio_pin_status()
189 				val = readl(&slcr_base->mio_pin  in zynq_slcr_get_mio_pin_status()
190 						[mio_ptr->get_pins[j]]);  in zynq_slcr_get_mio_pin_status()
191 				if ((val & mio_ptr->mask) == mio_ptr->check_val)  in zynq_slcr_get_mio_pin_status()