Lines Matching +full:0 +full:x61840000
13 #define SC_BASE_ADDR 0x61840000
15 #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
16 #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
17 #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
19 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
20 #define SC_DPLLCTRL_SSC_EN (0x1 << 31)
21 #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
22 #define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
24 #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
25 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
27 #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
28 #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
29 #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
31 #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
33 #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
34 #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
35 #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
37 #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
38 #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
39 #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
41 #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
42 #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
43 #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
44 #define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
45 #define SC_RSTCTRL_NRST_GIO (0x1 << 6)
47 #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
48 #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
49 #define SC_RSTCTRL_NRST_NAND (0x1 << 2)
51 #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
52 #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
53 #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
55 #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
58 #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
59 #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
60 #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
61 #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
62 #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
63 #define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
64 #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
65 #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
67 #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
69 #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
71 #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
72 #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
73 #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
74 #define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
75 #define SC_CLKCTRL_CEN_GIO (0x1 << 6)
77 #define SC_CLKCTRL_CEN_UMC (0x1 << 4)
78 #define SC_CLKCTRL_CEN_NAND (0x1 << 2)
79 #define SC_CLKCTRL_CEN_SBC (0x1 << 1)
80 #define SC_CLKCTRL_CEN_PERI (0x1 << 0)
83 #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
84 #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
85 #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
86 #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
87 #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
90 #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
91 #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
92 #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)