38 static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
39 static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
40 static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
41 static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x15171e45, 0x18182357};
42 static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
43 static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x35a00d88, 0x39e40e88};
44 static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x2288cc2c, 0x228a04d0};
45 static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x50005e00, 0x50006a00};
46 static u32 ddrphy_dtpr3[DRAM_FREQ_NR] = {0x0010cb49, 0x0010ec89};
47 static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000115, 0x00000125};
48 static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
51 static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
100 	ddrphy_vt_ctrl(phy_base, 0);  in ddrphy_dqs_delay_fixup()
102 	for (dx = 0; dx < nr_dx; dx++) {  in ddrphy_dqs_delay_fixup()
104 		rdqsd = (lcdlr1 >> 8) & 0xff;  in ddrphy_dqs_delay_fixup()
105 		rdqsd = clamp(rdqsd + step, 0U, 0xffU);  in ddrphy_dqs_delay_fixup()
106 		lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);  in ddrphy_dqs_delay_fixup()
121 	int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;  in ddrphy_get_system_latency()
123 	for (dx = 0; dx < nr_dx; dx++) {  in ddrphy_get_system_latency()
125 		for (rank = 0; rank < 4; rank++) {  in ddrphy_get_system_latency()
126 			dgsl = gtr & 0x7;  in ddrphy_get_system_latency()
158 	writel(0x07d81e37, phy_base + MPHY_PGCR0);  in ddrphy_init()
159 	writel(0x0200c4e0, phy_base + MPHY_PGCR1);  in ddrphy_init()
168 	writel(0x00083def, phy_base + MPHY_PTR2);  in ddrphy_init()
174 	writel(0x55555555, phy_base + MPHY_ACIOCR1);  in ddrphy_init()
175 	writel(0x00000000, phy_base + MPHY_ACIOCR2);  in ddrphy_init()
176 	writel(0x55555555, phy_base + MPHY_ACIOCR3);  in ddrphy_init()
177 	writel(0x00000000, phy_base + MPHY_ACIOCR4);  in ddrphy_init()
178 	writel(0x00000055, phy_base + MPHY_ACIOCR5);  in ddrphy_init()
179 	writel(0x00181aa4, phy_base + MPHY_DXCCR);  in ddrphy_init()
181 	writel(0x0024641e, phy_base + MPHY_DSGCR);  in ddrphy_init()
182 	writel(0x0000040b, phy_base + MPHY_DCR);  in ddrphy_init()
188 	writel(0x00000006, phy_base + MPHY_MR1);  in ddrphy_init()
190 	writel(0x00000000, phy_base + MPHY_MR3);  in ddrphy_init()
192 	tmp = 0;  in ddrphy_init()
193 	for (dx = 0; dx < nr_dx; dx++)  in ddrphy_init()
195 	writel(0x90003087 | tmp, phy_base + MPHY_DTCR);  in ddrphy_init()
197 	writel(0x00000000, phy_base + MPHY_DTAR0);  in ddrphy_init()
198 	writel(0x00000008, phy_base + MPHY_DTAR1);  in ddrphy_init()
199 	writel(0x00000010, phy_base + MPHY_DTAR2);  in ddrphy_init()
200 	writel(0x00000018, phy_base + MPHY_DTAR3);  in ddrphy_init()
201 	writel(0xdd22ee11, phy_base + MPHY_DTDR0);  in ddrphy_init()
202 	writel(0x7788bb44, phy_base + MPHY_DTDR1);  in ddrphy_init()
205 	writel(0x04048900, phy_base + MPHY_ZQCR);  in ddrphy_init()
208 	for (zq = 0; zq < 4; zq++) {  in ddrphy_init()
211 		 * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D  in ddrphy_init()
213 		writel(0x0007BB5D, zq_base + MPHY_ZQ_PR);  in ddrphy_init()
219 	for (dx = 0; dx < 4; dx++) {  in ddrphy_init()
226 		writel(0x00000000, dx_base + MPHY_DX_GCR1);  in ddrphy_init()
227 		writel(0x00000000, dx_base + MPHY_DX_GCR2);  in ddrphy_init()
228 		writel(0x00000000, dx_base + MPHY_DX_GCR3);  in ddrphy_init()
260 		0,
319 	unsigned long start = 0;  in __ddrphy_training()
322 	start = get_timer(0);  in __ddrphy_training()
333 		if (--timeout < 0) {  in __ddrphy_training()
352 	return 0;  in __ddrphy_training()
379 	return 0;  in ddrphy_impedance_calibration()
393 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
398 static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
399 static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
401 	{0x004A071D, 0x0078071D},
402 	{0x0055081E, 0x0089081E},
405 static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
407 static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
408 static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
426 	if (latency > 0xf) {  in umc_set_system_latency()
427 		val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;  in umc_set_system_latency()
428 		val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;  in umc_set_system_latency()
458 	writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);  in umc_ud_init()
461 		writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);  in umc_ud_init()
472 	case 0:  in umc_dc_init()
473 		return 0;  in umc_dc_init()
481 		pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",  in umc_dc_init()
494 	val = 0x000e000e;  in umc_dc_init()
500 	if (latency > 0xf) {  in umc_dc_init()
501 		val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;  in umc_dc_init()
502 		val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;  in umc_dc_init()
511 	writel(0x04060A02, dc_base + UMC_WDATACTL_D0);  in umc_dc_init()
513 		writel(0x04060A02, dc_base + UMC_WDATACTL_D1);  in umc_dc_init()
514 	writel(0x04000000, dc_base + UMC_DATASET);  in umc_dc_init()
515 	writel(0x00400020, dc_base + UMC_DCCGCTL);  in umc_dc_init()
516 	writel(0x00000084, dc_base + UMC_FLOWCTLG);  in umc_dc_init()
517 	writel(0x00000000, dc_base + UMC_ACSSETA);  in umc_dc_init()
522 	writel(0x00004400, dc_base + UMC_FLOWCTLC);  in umc_dc_init()
523 	writel(0x200A0A00, dc_base + UMC_SPCSETB);  in umc_dc_init()
524 	writel(0x00000520, dc_base + UMC_DFICUPDCTLA);  in umc_dc_init()
525 	writel(0x0000000D, dc_base + UMC_RESPCTL);  in umc_dc_init()
528 		writel(0x00202000, dc_base + UMC_FLOWCTLB);  in umc_dc_init()
529 		writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);  in umc_dc_init()
530 		writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);  in umc_dc_init()
531 		writel(0x00080700, dc_base + UMC_BSICMAPSET);  in umc_dc_init()
533 		writel(0x00200000, dc_base + UMC_FLOWCTLB);  in umc_dc_init()
534 		writel(0x00000000, dc_base + UMC_BSICMAPSET);  in umc_dc_init()
537 	writel(0x00000000, dc_base + UMC_ERRMASKA);  in umc_dc_init()
538 	writel(0x00000000, dc_base + UMC_ERRMASKB);  in umc_dc_init()
540 	return 0;  in umc_dc_init()
546 	void __iomem *dc_base = umc_ch_base + 0x00011000;  in umc_ch_init()
547 	void __iomem *phy_base = umc_ch_base + 0x00030000;  in umc_ch_init()
550 	writel(0x00000002, dc_base + UMC_INITSET);  in umc_ch_init()
587 	umc_refresh_ctrl(dc_base, 0);  in umc_ch_init()
593 	return 0;  in umc_ch_init()
598 	writel(0x000000ff, um_base + UMC_MBUS0);  in um_init()
599 	writel(0x000000ff, um_base + UMC_MBUS1);  in um_init()
600 	writel(0x000000ff, um_base + UMC_MBUS2);  in um_init()
601 	writel(0x000000ff, um_base + UMC_MBUS3);  in um_init()
606 	void __iomem *um_base = (void __iomem *)0x5b600000;  in uniphier_pxs2_umc_init()
607 	void __iomem *umc_ch_base = (void __iomem *)0x5b800000;  in uniphier_pxs2_umc_init()
623 	for (ch = 0; ch < DRAM_CH_NR; ch++) {  in uniphier_pxs2_umc_init()
636 		umc_ch_base += 0x00200000;  in uniphier_pxs2_umc_init()
641 	return 0;  in uniphier_pxs2_umc_init()