mach-tegra/tegra30/cpu.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
11 #include <asm/arch-tegra/clk_rst.h>
12 #include <asm/arch-tegra/pmc.h>
13 #include <asm/arch-tegra/tegra_i2c.h>
16 /* Tegra30-specific CPU init code */
21 	writel(addr, &reg->cmd_addr0);  in tegra_i2c_ll_write_addr()
22 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_addr()
29 	writel(data, &reg->cmd_data1);  in tegra_i2c_ll_write_data()
30 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_data()
54 	reg = readl(&pmc->pmc_cntrl);  in enable_cpu_power_rail()
56 	writel(reg, &pmc->pmc_cntrl);  in enable_cpu_power_rail()
70 	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.  in enable_cpu_power_rail()
82  * the dvc i2c, turning on mselect and selecting the G CPU cluster
93 	clrbits_le32(flow->cluster_control, 1 << 0);  in t30_init_clocks()
95 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);  in t30_init_clocks()
101 	writel(val, &clkrst->crc_clk_sys_rate);  in t30_init_clocks()
113 	 * Our high-level clock routines are not available prior to  in t30_init_clocks()
114 	 * relocation. We use the low-level functions which require a  in t30_init_clocks()
115 	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)  in t30_init_clocks()
133 	writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);  in set_cpu_running()
157 	 *  if it's a non-zero value.  in start_cpu()