Lines Matching refs:padctl_writel

105 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
111 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
117 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
136 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
142 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
148 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
226 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
231 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
235 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
239 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
243 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
250 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
256 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
260 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
264 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
270 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
274 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
293 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
312 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
331 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
349 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
367 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
378 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
382 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
386 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()