Lines Matching refs:value
98 u32 value; in tegra_xusb_padctl_enable() local
103 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
104 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra_xusb_padctl_enable()
105 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
109 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
110 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra_xusb_padctl_enable()
111 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
115 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
116 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra_xusb_padctl_enable()
117 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
124 u32 value; in tegra_xusb_padctl_disable() local
134 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
135 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra_xusb_padctl_disable()
136 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
140 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
141 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra_xusb_padctl_disable()
142 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
146 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
147 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra_xusb_padctl_disable()
148 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
219 u32 value; in pcie_phy_enable() local
223 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
224 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK; in pcie_phy_enable()
225 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); in pcie_phy_enable()
226 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
228 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
229 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK; in pcie_phy_enable()
230 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a); in pcie_phy_enable()
231 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
233 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
234 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; in pcie_phy_enable()
235 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
237 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
238 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; in pcie_phy_enable()
239 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
241 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
242 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; in pcie_phy_enable()
243 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
245 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
246 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK; in pcie_phy_enable()
247 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK; in pcie_phy_enable()
248 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2); in pcie_phy_enable()
249 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN; in pcie_phy_enable()
250 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
252 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
253 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK; in pcie_phy_enable()
254 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK; in pcie_phy_enable()
255 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25); in pcie_phy_enable()
256 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
258 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
259 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; in pcie_phy_enable()
260 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
262 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
263 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; in pcie_phy_enable()
264 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
268 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
269 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN; in pcie_phy_enable()
270 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
272 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
273 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; in pcie_phy_enable()
274 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
281 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
282 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) in pcie_phy_enable()
285 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) { in pcie_phy_enable()
291 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
292 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; in pcie_phy_enable()
293 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
300 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
301 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) in pcie_phy_enable()
304 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) { in pcie_phy_enable()
310 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
311 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; in pcie_phy_enable()
312 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
318 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
319 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) in pcie_phy_enable()
322 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) { in pcie_phy_enable()
328 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
329 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; in pcie_phy_enable()
330 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; in pcie_phy_enable()
331 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
337 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
338 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) in pcie_phy_enable()
341 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) { in pcie_phy_enable()
347 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
348 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; in pcie_phy_enable()
349 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
355 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
356 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) in pcie_phy_enable()
359 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) { in pcie_phy_enable()
365 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
366 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; in pcie_phy_enable()
367 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
369 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
370 value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; in pcie_phy_enable()
371 value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; in pcie_phy_enable()
372 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; in pcie_phy_enable()
373 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; in pcie_phy_enable()
374 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
376 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
377 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; in pcie_phy_enable()
378 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
380 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
381 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; in pcie_phy_enable()
382 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
384 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
385 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; in pcie_phy_enable()
386 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
390 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
391 value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; in pcie_phy_enable()
392 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()