1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2013-2015
7 /* Tegra210 Clock control functions */
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21  * Clock types that we can use as a source. The Tegra210 has muxes for the
50 	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
59 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
124 	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
350  *	SPDIF - which is both 0x08 and 0x0c
353 #define NONE(name) (-1)
583 	NONE(DPAUX),
597 	/* Y: 192 (192 - 223) */
679 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
707 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
711 	assert(internal_id != -1);  in get_periph_source_reg()
715 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
719 		internal_id -= PERIPHC_VW_FIRST;  in get_periph_source_reg()
720 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
725 		internal_id -= PERIPHC_X_FIRST;  in get_periph_source_reg()
726 		return &clkrst->crc_clk_src_x[internal_id];  in get_periph_source_reg()
730 	internal_id -= PERIPHC_Y_FIRST;  in get_periph_source_reg()
731 	return &clkrst->crc_clk_src_y[internal_id];  in get_periph_source_reg()
740 		return -1;  in get_periph_clock_info()
744 		return -1;  in get_periph_clock_info()
748 		return -1;  in get_periph_clock_info()
789  * @return mux value (0-4, or -1 if not found)
807 	return -1;  in get_periph_clock_source()
820 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
822 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
824 		clk = &clkrst->crc_clk_out_enb_x;  in clock_set_enable()
826 		clk = &clkrst->crc_clk_out_enb_y;  in clock_set_enable()
846 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
848 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
850 		reset = &clkrst->crc_rst_devices_x;  in reset_set_enable()
852 		reset = &clkrst->crc_rst_devices_y;  in reset_set_enable()
868  * @param clk_id    Clock ID according to tegra210 device tree binding
931  * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
944 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra210_setup_pllp()
948 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra210_setup_pllp()
953 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra210_setup_pllp()
959 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra210_setup_pllp()
1015 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,  in clock_early_init()
1023 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],  in clock_early_init()
1028 	data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);  in clock_early_init()
1029 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()
1038 	value = readl(&clkrst->crc_spare_reg0);  in clk_m_get_rate()
1057 	writel(freq, &sysctr->cntfid0);  in arch_timer_init()
1059 	val = readl(&sysctr->cntcr);  in arch_timer_init()
1061 	writel(val, &sysctr->cntcr);  in arch_timer_init()
1086 	 * Recovery Mode or Boot from USB", sub-section "PLLREFE".  in tegra_pllref_enable()
1111 		return -ETIMEDOUT;  in tegra_pllref_enable()
1161 	 * Recovery Mode or Boot from USB", sub-section "PLLEs".  in tegra_plle_enable()
1213 		return -ETIMEDOUT;  in tegra_plle_enable()
1280 	{ -1, },