1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/pinmux.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/pmc.h>
16 #include <asm/arch-tegra/ap.h>
19 /* Tegra124-specific CPU init code */
27 	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */  in enable_cpu_power_rail()
34 	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),  in enable_cpu_power_rail()
37 	writel(0x7C830, &pmc->pmc_cpupwrgood_timer);  in enable_cpu_power_rail()
40 	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);  in enable_cpu_power_rail()
41 	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);  in enable_cpu_power_rail()
52 	/* Wait for PLL-X to lock */  in enable_cpu_clocks()
54 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in enable_cpu_clocks()
56 	} while ((reg & (1 << pllinfo->lock_det)) == 0);  in enable_cpu_clocks()
63 	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);  in enable_cpu_clocks()
64 	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);  in enable_cpu_clocks()
70 	writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);  in enable_cpu_clocks()
90 	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
91 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
93 	/* Clear the SW-controlled reset of the slow cluster */  in remove_cpu_resets()
96 	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
98 	/* Clear the SW-controlled reset of the fast cluster */  in remove_cpu_resets()
104 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
117 	clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN);  in tegra124_ram_repair()
121 	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);  in tegra124_ram_repair()
126 		val = readl(&flow->ram_repair);  in tegra124_ram_repair()
127 	} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);  in tegra124_ram_repair()
132 	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);  in tegra124_ram_repair()
137 		val = readl(&flow->ram_repair_cluster1);  in tegra124_ram_repair()
138 	} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);  in tegra124_ram_repair()
145  * Tegra124 requires some special clock initialization, including setting up
159 	clrbits_le32(&flow->cluster_control, 1);  in tegra124_init_clocks()
162 	val = readl(&clkrst->crc_osc_ctrl);  in tegra124_init_clocks()
165 	writel(val, &clkrst->crc_osc_ctrl);  in tegra124_init_clocks()
168 	val = readl(&pmc->pmc_osc_edpd_over);  in tegra124_init_clocks()
171 	writel(val, &pmc->pmc_osc_edpd_over);  in tegra124_init_clocks()
174 	setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);  in tegra124_init_clocks()
180 	writel(val, &clkrst->crc_clk_sys_rate);  in tegra124_init_clocks()
182 	/* Enable clocks to required peripherals. TBD - minimize this list */  in tegra124_init_clocks()
237 	reg = readl(&pmc->pmc_pwrgate_status);  in is_partition_powered()
248 		/* No, toggle the partition power state (OFF -> ON) */  in power_partition()
250 		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);  in power_partition()
270 	/* Power up the fast cluster non-CPU partition */  in powerup_cpus()
289 	/* Set power-gating timer multiplier */  in start_cpu()
291 	       &pmc->pmc_pwrgate_timer_mult);  in start_cpu()