25 	debug("%s entry\n", __func__);  in enable_cpu_power_rail()
50 	debug("%s entry\n", __func__);  in enable_cpu_clocks()
55 		debug("%s: PLLX base = 0x%08X\n", __func__, reg);  in enable_cpu_clocks()
58 	debug("%s: PLLX locked, delay for stable clocks\n", __func__);  in enable_cpu_clocks()
62 	debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);  in enable_cpu_clocks()
66 	debug("%s: Enabling clock to all CPUs\n", __func__);  in enable_cpu_clocks()
72 	debug("%s: Enabling main CPU complex clocks\n", __func__);  in enable_cpu_clocks()
78 	debug("%s: Done\n", __func__);  in enable_cpu_clocks()
86 	debug("%s entry\n", __func__);  in remove_cpu_resets()
129 		debug("Ram Repair cluster0 failed\n");  in tegra124_ram_repair()
141 		debug("Ram Repair cluster1 failed\n");  in tegra124_ram_repair()
156 	debug("%s entry\n", __func__);  in tegra124_init_clocks()
176 	debug("Setting up PLLX\n");  in tegra124_init_clocks()
183 	debug("Enabling clocks\n");  in tegra124_init_clocks()
215 	debug("Taking periphs out of reset\n");  in tegra124_init_clocks()
228 	debug("%s exit\n", __func__);  in tegra124_init_clocks()
245 	debug("%s: part ID = %08X\n", __func__, partid);  in power_partition()
249 		debug("power_partition, toggling state\n");  in power_partition()
264 	debug("%s entry: G cluster\n", __func__);  in powerup_cpus()
267 	debug("%s: CRAIL\n", __func__);  in powerup_cpus()
271 	debug("%s: C0NC\n", __func__);  in powerup_cpus()
275 	debug("%s: CE0\n", __func__);  in powerup_cpus()
278 	debug("%s: done\n", __func__);  in powerup_cpus()
285 	debug("%s entry, reset_vector = %x\n", __func__, reset_vector);  in start_cpu()
300 	debug("%s exit, should continue @ reset_vector\n", __func__);  in start_cpu()