324 #define OFFSET(name, value) PERIPHC_ ## name  argument
964 	u32 value;  in tegra_plle_enable()  local
966 	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);  in tegra_plle_enable()
967 	value &= ~PLLE_BASE_LOCK_OVERRIDE;  in tegra_plle_enable()
968 	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);  in tegra_plle_enable()
970 	value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);  in tegra_plle_enable()
971 	value |= PLLE_AUX_ENABLE_SWCTL;  in tegra_plle_enable()
972 	value &= ~PLLE_AUX_SEQ_ENABLE;  in tegra_plle_enable()
973 	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);  in tegra_plle_enable()
977 	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);  in tegra_plle_enable()
978 	value |= PLLE_MISC_IDDQ_SWCTL;  in tegra_plle_enable()
979 	value &= ~PLLE_MISC_IDDQ_OVERRIDE;  in tegra_plle_enable()
980 	value |= PLLE_MISC_LOCK_ENABLE;  in tegra_plle_enable()
981 	value |= PLLE_MISC_PTS;  in tegra_plle_enable()
982 	value |= PLLE_MISC_VREG_BG_CTRL(3);  in tegra_plle_enable()
983 	value |= PLLE_MISC_VREG_CTRL(2);  in tegra_plle_enable()
984 	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);  in tegra_plle_enable()
988 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
989 	value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |  in tegra_plle_enable()
991 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
993 	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);  in tegra_plle_enable()
994 	value &= ~PLLE_BASE_PLDIV_CML(0xf);  in tegra_plle_enable()
995 	value &= ~PLLE_BASE_NDIV(0xff);  in tegra_plle_enable()
996 	value &= ~PLLE_BASE_MDIV(0xff);  in tegra_plle_enable()
997 	value |= PLLE_BASE_PLDIV_CML(cpcon);  in tegra_plle_enable()
998 	value |= PLLE_BASE_NDIV(n);  in tegra_plle_enable()
999 	value |= PLLE_BASE_MDIV(m);  in tegra_plle_enable()
1000 	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);  in tegra_plle_enable()
1004 	value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);  in tegra_plle_enable()
1005 	value |= PLLE_BASE_ENABLE;  in tegra_plle_enable()
1006 	writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);  in tegra_plle_enable()
1011 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
1012 	value &= ~PLLE_SS_CNTL_SSCINVERT;  in tegra_plle_enable()
1013 	value &= ~PLLE_SS_CNTL_SSCCENTER;  in tegra_plle_enable()
1015 	value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);  in tegra_plle_enable()
1016 	value &= ~PLLE_SS_CNTL_SSCINC(0xff);  in tegra_plle_enable()
1017 	value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);  in tegra_plle_enable()
1019 	value |= PLLE_SS_CNTL_SSCINCINTR(0x20);  in tegra_plle_enable()
1020 	value |= PLLE_SS_CNTL_SSCINC(0x01);  in tegra_plle_enable()
1021 	value |= PLLE_SS_CNTL_SSCMAX(0x25);  in tegra_plle_enable()
1023 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
1025 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
1026 	value &= ~PLLE_SS_CNTL_SSCBYP;  in tegra_plle_enable()
1027 	value &= ~PLLE_SS_CNTL_BYPASS_SS;  in tegra_plle_enable()
1028 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
1032 	value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
1033 	value &= ~PLLE_SS_CNTL_INTERP_RESET;  in tegra_plle_enable()
1034 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);  in tegra_plle_enable()
1141 	u32 value;  in clock_set_up_plldp()  local
1143 	value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;  in clock_set_up_plldp()
1144 	writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);  in clock_set_up_plldp()
1146 	writel(value, &clkrst->crc_plldp_ss_cfg);  in clock_set_up_plldp()