1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2013-2015
7 /* Tegra124 Clock control functions */
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20  * Clock types that we can use as a source. The Tegra124 has muxes for the
49 	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
57 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
122 	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
320  *	SPDIF - which is both 0x08 and 0x0c
323 #define NONE(name) (-1)
497 	NONE(CEC),
610 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
628 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
632 	assert(internal_id != -1);  in get_periph_source_reg()
634 		internal_id -= PERIPHC_X_FIRST;  in get_periph_source_reg()
635 		return &clkrst->crc_clk_src_x[internal_id];  in get_periph_source_reg()
637 		internal_id -= PERIPHC_VW_FIRST;  in get_periph_source_reg()
638 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
640 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
650 		return -1;  in get_periph_clock_info()
654 		return -1;  in get_periph_clock_info()
658 		return -1;  in get_periph_clock_info()
699  * @return mux value (0-4, or -1 if not found)
717 	return -1;  in get_periph_clock_source()
730 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
732 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
734 		clk = &clkrst->crc_clk_out_enb_x;  in clock_set_enable()
753 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
755 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
757 		reset = &clkrst->crc_rst_devices_x;  in reset_set_enable()
772  * @param clk_id    Clock ID according to tegra124 device tree binding
845 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);  in clock_early_init()
878 	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);  in clock_early_init()
882 	setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));  in clock_early_init()
887 	data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);  in clock_early_init()
888 	data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);  in clock_early_init()
889 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()
894  * clock_early_init_done - Check if clock_early_init() has been called
906 	val = readl(&clkrst->crc_sclk_brst_pol);  in clock_early_init_done()
924 	writel(freq, &sysctr->cntfid0);  in arch_timer_init()
926 	val = readl(&sysctr->cntcr);  in arch_timer_init()
928 	writel(val, &sysctr->cntcr);  in arch_timer_init()
1045 	/* uses PLLP, has a non-standard bit layout. */  in clock_sor_enable_edp_clock()
1097 		diff = vco - divn * cf;  in clock_set_display_rate()
1100 			diff = cf - diff;  in clock_set_display_rate()
1144 	writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);  in clock_set_up_plldp()
1146 	writel(value, &clkrst->crc_plldp_ss_cfg);  in clock_set_up_plldp()
1155 		return &clkrst->plldp;  in clock_get_simple_pll()
1180 	{ -1, },